From 2302fa37d54a607ebfed5ddf397e0c6448eb5f2d Mon Sep 17 00:00:00 2001 From: Cary R Date: Fri, 27 Feb 2026 21:17:09 -0800 Subject: [PATCH] Add V13 release notes --- Documentation/index.rst | 1 + Documentation/releases/index.rst | 10 ++ Documentation/releases/v13-0-release-note.rst | 98 +++++++++++++++++++ Documentation/targets/tgt-sizer.rst | 2 +- Documentation/usage/waveform_viewer.rst | 1 - 5 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 Documentation/releases/index.rst create mode 100644 Documentation/releases/v13-0-release-note.rst diff --git a/Documentation/index.rst b/Documentation/index.rst index 0a135f95e..251802811 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -12,6 +12,7 @@ Welcome to the documentation for Icarus Verilog. :maxdepth: 2 :caption: Contents: + releases/index usage/index targets/index developer/index diff --git a/Documentation/releases/index.rst b/Documentation/releases/index.rst new file mode 100644 index 000000000..3b72b78f0 --- /dev/null +++ b/Documentation/releases/index.rst @@ -0,0 +1,10 @@ +Icarus Verilog Release Notes +============================ + +This section contains the release notes for all releases after and including +V13.0. Older release notes can be found here: ``__ + +.. toctree:: + :maxdepth: 1 + + v13-0-release-note diff --git a/Documentation/releases/v13-0-release-note.rst b/Documentation/releases/v13-0-release-note.rst new file mode 100644 index 000000000..8be922952 --- /dev/null +++ b/Documentation/releases/v13-0-release-note.rst @@ -0,0 +1,98 @@ +🎉 Release V13.0 +================ + +The Icarus Verilog development team is pleased to announce **Release V13** of Icarus Verilog. + +Release V13 builds on the V12 series with a focus on correctness, runtime stability, improved +diagnostics, and incremental standard conformance improvements. + +---- + +🐞 Bug Fix Summary +------------------ + +Release V13 resolves numerous issues reported against V12, including: + +* Incorrect signed constant handling. +* Generate block naming collisions. +* Elaboration-time assertion failures. +* Runtime crashes in malformed corner cases. +* Memory management issues during elaboration and simulation. + + +---- + +🔄 Major Changes in V13 +======================= + +🧠 Language & Elaboration Fixes +------------------------------- + +Release V13 includes multiple fixes to elaboration and expression handling: + +* Resolved generate block scope resolution issues affecting nested and conditional generate constructs. +* Corrected signed arithmetic corner cases, including shift and width propagation behavior. +* Fixed constant expression evaluation inconsistencies during parameter elaboration. +* Improved handling of packed and unpacked arrays in assignments and port binding corner cases. +* Addressed elaboration-time assertion failures triggered by malformed or ambiguous constructs. +* Corrected several source-location reporting issues for elaboration errors. + +These changes improve standards conformance and eliminate behavioral inconsistencies observed in the V12 series. + +---- + +⚙️ Simulator (vvp) Improvements +------------------------------- + +The `vvp` runtime engine has received internal stability and correctness updates: + +* Improved event scheduling behavior in zero-delay and non-blocking assignment scenarios. +* Fixed race-condition corner cases uncovered by expanded regression testing. +* Eliminated memory leaks affecting long-running or large simulations. +* Resolved crash conditions caused by invalid internal state transitions. +* Improved robustness of `$dumpvars` handling in large hierarchical designs. +* General runtime consistency and determinism improvements. + +`vvp` continues to enforce version matching between the runtime and generated bytecode. Designs +must be recompiled after upgrading. + +---- + +🔌 VPI Updates +-------------- + +Fixes improve VPI reliability and conformance: + +* Corrected hierarchical object lookup behavior in specific corner cases. +* Improved stability of callback registration during startup and shutdown. +* Fixed invalid handle dereference scenarios that could result in segmentation faults. +* Addressed inconsistencies in VPI object property reporting. + +---- + +🛠 Diagnostics & Toolchain +-------------------------- + +* Improved clarity and consistency of error and warning messages. +* Better reporting of width mismatches and implicit net declarations. +* More accurate diagnostic source locations. +* Build system updates for compatibility with modern compiler toolchains. +* Regression suite expansion and CI validation improvements. + +---- + +📦 Upgrade Notes +---------------- + +* Recompile all designs when upgrading from V12 or any other prior version. +* Review warnings carefully; improved diagnostics may expose previously silent issues. +* The only known breaking change is that wires must now be declared before use; which is required in the standard (see `gh1287 `__). + +---- + +🙏 Acknowledgments +------------------ + +We thank all contributors who reported issues, submitted patches, expanded regression coverage, and +improved documentation. Release 13 reflects continued community effort toward improving correctness, +stability, and maintainability. diff --git a/Documentation/targets/tgt-sizer.rst b/Documentation/targets/tgt-sizer.rst index b0bd3775f..a28768ad5 100644 --- a/Documentation/targets/tgt-sizer.rst +++ b/Documentation/targets/tgt-sizer.rst @@ -1,6 +1,6 @@ The sizer Code Analyzer (-tsizer) -=============================== +================================= The sizer target does not generate any code. Instead it will print statistics about the Verilog code. diff --git a/Documentation/usage/waveform_viewer.rst b/Documentation/usage/waveform_viewer.rst index 9c24c99ec..01840c0df 100644 --- a/Documentation/usage/waveform_viewer.rst +++ b/Documentation/usage/waveform_viewer.rst @@ -1,4 +1,3 @@ - Viewing Waveforms =================