From 1ee189630ba492d3eef6643b342c932e358d25b6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 14 Sep 2022 22:17:23 +0200 Subject: [PATCH] Fix module_output_port_list_def test The module_output_port_list_def declares a output port with an implicit data type and assigns an initial value to it. Since output ports with an implicit data type are nets this test is not standard compliant. This only works because at the moment the parser incorrectly flags all output ports with an initial value as variables rather than following the method defined by the standard to decide whether the port should be a net or variable. Make the test standard compliant by using an explicit data type for the output port, in which case it will be a variable. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_output_port_list_def.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ivtest/ivltests/module_output_port_list_def.v b/ivtest/ivltests/module_output_port_list_def.v index d40f453fe..6777e5b31 100644 --- a/ivtest/ivltests/module_output_port_list_def.v +++ b/ivtest/ivltests/module_output_port_list_def.v @@ -2,7 +2,7 @@ // output port declaration list. module M ( - output [31:0] x = 1, y = 2 + output reg [31:0] x = 1, y = 2 ); `define check(val, exp) \