diff --git a/tgt-vvp/draw_ufunc.c b/tgt-vvp/draw_ufunc.c
index bc95b431a..42a561d0a 100644
--- a/tgt-vvp/draw_ufunc.c
+++ b/tgt-vvp/draw_ufunc.c
@@ -32,7 +32,7 @@ static void function_argument_logic(ivl_signal_t port, ivl_expr_t expr)
       ewidth = ivl_expr_width(expr);
       pwidth = ivl_signal_width(port);
 
-      draw_eval_vec4(expr, 0);
+      draw_eval_vec4(expr);
       if (ewidth < pwidth)
 	    fprintf(vvp_out, "    %%pad/u %u;\n", pwidth);
 
diff --git a/tgt-vvp/draw_vpi.c b/tgt-vvp/draw_vpi.c
index d326dcf19..8e7f21642 100644
--- a/tgt-vvp/draw_vpi.c
+++ b/tgt-vvp/draw_vpi.c
@@ -387,7 +387,7 @@ static void draw_vpi_taskfunc_args(const char*call_string,
 	    switch (ivl_expr_value(expr)) {
 		case IVL_VT_LOGIC:
 		case IVL_VT_BOOL:
-		  draw_eval_vec4(expr, 0);
+		  draw_eval_vec4(expr);
 		  args[idx].vec_flag = ivl_expr_signed(expr)? 's' : 'u';
 		  args[idx].str_flag = 0;
 		  args[idx].real_flag = 0;
diff --git a/tgt-vvp/eval_bool.c b/tgt-vvp/eval_bool.c
index 414ba146e..f8817b38a 100644
--- a/tgt-vvp/eval_bool.c
+++ b/tgt-vvp/eval_bool.c
@@ -48,7 +48,7 @@ static int eval_bool64_logic(ivl_expr_t expr)
       int res;
       const char*s_flag = "";
 
-      draw_eval_vec4(expr, STUFF_OK_XZ);
+      draw_eval_vec4(expr);
       res = allocate_word();
       if (ivl_expr_signed(expr))
 	    s_flag = "/s";
diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c
index b19d2a225..5579ecf7d 100644
--- a/tgt-vvp/eval_expr.c
+++ b/tgt-vvp/eval_expr.c
@@ -230,7 +230,7 @@ void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
 			   variable array. In this case, the ix/getv
 			   will not work, so do it the hard way. */
 		      if (ivl_signal_type(sig) == IVL_SIT_REG) {
-			    draw_eval_vec4(expr, 0);
+			    draw_eval_vec4(expr);
 			    fprintf(vvp_out, "    %%ix/vec4%s %u;\n", type, ix);
 			    break;
 		      }
@@ -240,7 +240,7 @@ void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
 		            assert(! number_is_unknown(ixe));
 		            word = get_number_immediate(ixe);
 		      } else {
-		            draw_eval_vec4(expr, 0);
+		            draw_eval_vec4(expr);
 		            fprintf(vvp_out, "    %%ix/vec4%s %u;\n", type, ix);
 		            break;
 		      }
@@ -252,7 +252,7 @@ void eval_logic_into_integer(ivl_expr_t expr, unsigned ix)
 	  }
 
 	  default:
-	    draw_eval_vec4(expr, 0);
+	    draw_eval_vec4(expr);
 	      /* Is this a signed expression? */
 	    if (ivl_expr_signed(expr)) {
 		  fprintf(vvp_out, "    %%ix/vec4/s %u;\n", ix);
@@ -2456,29 +2456,6 @@ static struct vector_info draw_ternary_expr(ivl_expr_t expr, unsigned wid)
       return res;
 }
 
-static struct vector_info draw_darray_pop(ivl_expr_t expr, unsigned wid)
-{
-      struct vector_info res;
-      ivl_expr_t arg;
-      const char*fb;
-
-      if (strcmp(ivl_expr_name(expr), "$ivl_darray_method$pop_back")==0)
-	    fb = "b";
-      else
-	    fb = "f";
-
-      res.base = allocate_vector(wid);
-      res.wid = wid;
-
-      arg = ivl_expr_parm(expr, 0);
-      assert(ivl_expr_type(arg) == IVL_EX_SIGNAL);
-
-      fprintf(vvp_out, "    %%qpop/%s v%p_0, %u, %u;\n", fb,
-	      ivl_expr_signal(arg), res.base, res.wid);
-
-      return res;
-}
-
 static struct vector_info draw_sfunc_expr(ivl_expr_t expr, unsigned wid)
 {
 #if 0
@@ -2517,6 +2494,7 @@ static struct vector_info draw_sfunc_expr(ivl_expr_t expr, unsigned wid)
       struct vector_info res;
       res.base = 0;
       res.wid = 0;
+      vvp_errors += 1;
       return res;
 #endif
 }
diff --git a/tgt-vvp/eval_object.c b/tgt-vvp/eval_object.c
index b90afc9ee..cce80207d 100644
--- a/tgt-vvp/eval_object.c
+++ b/tgt-vvp/eval_object.c
@@ -71,7 +71,7 @@ static int eval_darray_new(ivl_expr_t ex)
 	    switch (ivl_type_base(element_type)) {
 		case IVL_VT_BOOL:
 		  for (idx = 0 ; idx < ivl_expr_parms(init_expr) ; idx += 1) {
-			draw_eval_vec4(ivl_expr_parm(init_expr,idx), STUFF_OK_XZ);
+			draw_eval_vec4(ivl_expr_parm(init_expr,idx));
 			fprintf(vvp_out, "    %%ix/load 3, %u, 0;\n", idx);
 			fprintf(vvp_out, "    %%set/dar/obj/vec4 3;\n");
 			fprintf(vvp_out, "    %%pop/vec4 1;\n");
diff --git a/tgt-vvp/eval_real.c b/tgt-vvp/eval_real.c
index 6f6d75424..7a60bbe55 100644
--- a/tgt-vvp/eval_real.c
+++ b/tgt-vvp/eval_real.c
@@ -243,9 +243,9 @@ static void draw_realnum_real(ivl_expr_t expr)
  * The real value of a logic expression is the integer value of the
  * expression converted to real.
  */
-static void draw_real_logic_expr(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_real_logic_expr(ivl_expr_t expr)
 {
-      draw_eval_vec4(expr, stuff_ok_flag);
+      draw_eval_vec4(expr);
       const char*sign_flag = ivl_expr_signed(expr)? "/s" : "";
 
       if (ivl_expr_width(expr) > 64) {
@@ -296,7 +296,7 @@ static void draw_sfunc_real(ivl_expr_t expr)
 	      /* If the value of the sfunc is a vector, then evaluate
 		 it as a vector, then convert the result to a real
 		 (via an index register) for the result. */
-	    draw_real_logic_expr(expr, 0);
+	    draw_real_logic_expr(expr);
 	    break;
 
 	  default:
@@ -326,7 +326,7 @@ static void draw_signal_real(ivl_expr_t expr)
       ivl_signal_t sig = ivl_expr_signal(expr);
       switch (ivl_signal_data_type(sig)) {
 	  case IVL_VT_LOGIC:
-	    draw_real_logic_expr(expr, 0);
+	    draw_real_logic_expr(expr);
 	    return;
 	  case IVL_VT_REAL:
 	    draw_signal_real_real(expr);
@@ -354,7 +354,7 @@ static void draw_ternary_real(ivl_expr_t expr)
       int cond_flag = allocate_flag();
 
 	/* Evaluate the ternary condition. */
-      draw_eval_vec4(cond, STUFF_OK_XZ|STUFF_OK_RO);
+      draw_eval_vec4(cond);
       if (ivl_expr_width(cond) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
@@ -416,7 +416,7 @@ static void draw_unary_real(ivl_expr_t expr)
 	 * a real expression, so use vector evaluation and then convert
 	 * that result to a real value. */
       if ((ivl_expr_opcode(expr) == '~') || (ivl_expr_opcode(expr) == '!')) {
-	    draw_real_logic_expr(expr, STUFF_OK_XZ);
+	    draw_real_logic_expr(expr);
 	    return;
       }
 
@@ -425,7 +425,7 @@ static void draw_unary_real(ivl_expr_t expr)
       if (ivl_expr_opcode(expr) == 'r') { /* Cast an integer value to a real. */
 	    const char *suffix = "";
 	    assert(ivl_expr_value(sube) != IVL_VT_REAL);
-	    draw_eval_vec4(sube, STUFF_OK_XZ);
+	    draw_eval_vec4(sube);
 	    if (ivl_expr_signed(sube)) suffix = "/s";
 	    fprintf(vvp_out, "    %%cvt/rv%s;\n", suffix);
 	    return;
@@ -485,7 +485,7 @@ void draw_eval_real(ivl_expr_t expr)
 	 * result to a real value. This is required to get integer
 	 * division to work correctly. */
       if (ivl_expr_value(expr) != IVL_VT_REAL) {
-	    draw_real_logic_expr(expr, STUFF_OK_XZ);
+	    draw_real_logic_expr(expr);
 	    return;
       }
 
@@ -533,7 +533,7 @@ void draw_eval_real(ivl_expr_t expr)
 
 	  default:
 	    if (ivl_expr_value(expr) == IVL_VT_VECTOR) {
-		  draw_eval_vec4(expr, 0);
+		  draw_eval_vec4(expr);
 		  const char*sign_flag = ivl_expr_signed(expr)? "/s" : "";
 
 		  int res = allocate_word();
diff --git a/tgt-vvp/eval_vec4.c b/tgt-vvp/eval_vec4.c
index 233bd627d..17dda6068 100644
--- a/tgt-vvp/eval_vec4.c
+++ b/tgt-vvp/eval_vec4.c
@@ -38,7 +38,7 @@ void resize_vec4_wid(ivl_expr_t expr, unsigned wid)
 	    fprintf(vvp_out, "    %%pad/u %u;\n", wid);
 }
 
-static void draw_binary_vec4_arith(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4_arith(ivl_expr_t expr)
 {
       ivl_expr_t le = ivl_expr_oper1(expr);
       ivl_expr_t re = ivl_expr_oper2(expr);
@@ -54,11 +54,11 @@ static void draw_binary_vec4_arith(ivl_expr_t expr, int stuff_ok_flag)
 	   operands (and the result) be the same width. We further
 	   assume that the core has not given us an operand wider then
 	   the expression width. So padd operands as needed. */
-      draw_eval_vec4(le, stuff_ok_flag);
+      draw_eval_vec4(le);
       if (lwid != ewid) {
 	    fprintf(vvp_out, "    %%pad/%c %u;\n", ivl_expr_signed(le)? 's' : 'u', ewid);
       }
-      draw_eval_vec4(re, stuff_ok_flag);
+      draw_eval_vec4(re);
       if (rwid != ewid) {
 	    fprintf(vvp_out, "    %%pad/%c %u;\n", ivl_expr_signed(re)? 's' : 'u', ewid);
       }
@@ -94,10 +94,10 @@ static void draw_binary_vec4_arith(ivl_expr_t expr, int stuff_ok_flag)
       }
 }
 
-static void draw_binary_vec4_bitwise(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4_bitwise(ivl_expr_t expr)
 {
-      draw_eval_vec4(ivl_expr_oper1(expr), stuff_ok_flag);
-      draw_eval_vec4(ivl_expr_oper2(expr), stuff_ok_flag);
+      draw_eval_vec4(ivl_expr_oper1(expr));
+      draw_eval_vec4(ivl_expr_oper2(expr));
 
       switch (ivl_expr_opcode(expr)) {
 	  case '&':
@@ -243,7 +243,7 @@ static void draw_binary_vec4_compare_class(ivl_expr_t expr)
       vvp_errors += 1;
 }
 
-static void draw_binary_vec4_compare(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4_compare(ivl_expr_t expr)
 {
       ivl_expr_t le = ivl_expr_oper1(expr);
       ivl_expr_t re = ivl_expr_oper2(expr);
@@ -282,10 +282,10 @@ static void draw_binary_vec4_compare(ivl_expr_t expr, int stuff_ok_flag)
       if (ivl_expr_width(re) > use_wid)
 	    use_wid = ivl_expr_width(re);
 
-      draw_eval_vec4(le, stuff_ok_flag);
+      draw_eval_vec4(le);
       resize_vec4_wid(le, use_wid);
 
-      draw_eval_vec4(re, stuff_ok_flag);
+      draw_eval_vec4(re);
       resize_vec4_wid(re, use_wid);
 
       switch (ivl_expr_opcode(expr)) {
@@ -319,13 +319,13 @@ static void draw_binary_vec4_land(ivl_expr_t expr)
 
 	/* Push the left expression. Reduce it to a single bit if
 	   necessary. */
-      draw_eval_vec4(le, STUFF_OK_XZ);
+      draw_eval_vec4(le);
       if (ivl_expr_width(le) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
 	/* Now push the right expression. Again, reduce to a single
 	   bit if necessasry. */
-      draw_eval_vec4(re, STUFF_OK_XZ);
+      draw_eval_vec4(re);
       if (ivl_expr_width(re) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
@@ -423,7 +423,7 @@ static void draw_binary_vec4_le_string(ivl_expr_t expr)
       }
 }
 
-static void draw_binary_vec4_le(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4_le(ivl_expr_t expr)
 {
       ivl_expr_t le = ivl_expr_oper1(expr);
       ivl_expr_t re = ivl_expr_oper2(expr);
@@ -480,10 +480,10 @@ static void draw_binary_vec4_le(ivl_expr_t expr, int stuff_ok_flag)
       if (ivl_expr_width(re) > use_wid)
 	    use_wid = ivl_expr_width(re);
 
-      draw_eval_vec4(le, stuff_ok_flag);
+      draw_eval_vec4(le);
       resize_vec4_wid(le, use_wid);
 
-      draw_eval_vec4(re, stuff_ok_flag);
+      draw_eval_vec4(re);
       resize_vec4_wid(re, use_wid);
 
       switch (use_opcode) {
@@ -510,13 +510,13 @@ static void draw_binary_vec4_lor(ivl_expr_t expr)
 
 	/* Push the left expression. Reduce it to a single bit if
 	   necessary. */
-      draw_eval_vec4(le, STUFF_OK_XZ);
+      draw_eval_vec4(le);
       if (ivl_expr_width(le) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
 	/* Now push the right expression. Again, reduce to a single
 	   bit if necessasry. */
-      draw_eval_vec4(re, STUFF_OK_XZ);
+      draw_eval_vec4(re);
       if (ivl_expr_width(re) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
@@ -526,13 +526,13 @@ static void draw_binary_vec4_lor(ivl_expr_t expr)
 	    fprintf(vvp_out, "    %%pad/u %u;\n", ivl_expr_width(expr));
 }
 
-static void draw_binary_vec4_lrs(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4_lrs(ivl_expr_t expr)
 {
       ivl_expr_t le = ivl_expr_oper1(expr);
       ivl_expr_t re = ivl_expr_oper2(expr);
 
 	// Push the left expression onto the stack.
-      draw_eval_vec4(le, stuff_ok_flag);
+      draw_eval_vec4(le);
 
 	// Calculate the shift amount into an index register.
       int use_index_reg = allocate_word();
@@ -562,7 +562,7 @@ static void draw_binary_vec4_lrs(ivl_expr_t expr, int stuff_ok_flag)
       clr_word(use_index_reg);
 }
 
-static void draw_binary_vec4(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_binary_vec4(ivl_expr_t expr)
 {
       switch (ivl_expr_opcode(expr)) {
 	  case 'a': /* Logical && */
@@ -575,7 +575,7 @@ static void draw_binary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	  case '/':
 	  case '%':
 	  case 'p': /* ** (power) */
-	    draw_binary_vec4_arith(expr, stuff_ok_flag);
+	    draw_binary_vec4_arith(expr);
 	    break;
 
 	  case '&':
@@ -584,27 +584,27 @@ static void draw_binary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	  case 'A': /* NAND (~&) */
 	  case 'O': /* NOR  (~|) */
 	  case 'X': /* exclusive nor (~^) */
-	    draw_binary_vec4_bitwise(expr, stuff_ok_flag);
+	    draw_binary_vec4_bitwise(expr);
 	    break;
 
 	  case 'e': /* == */
 	  case 'E': /* === */
 	  case 'n': /* !== */
 	  case 'N': /* !== */
-	    draw_binary_vec4_compare(expr, stuff_ok_flag);
+	    draw_binary_vec4_compare(expr);
 	    break;
 
 	  case 'G': /* >= */
 	  case 'L': /* <= */
 	  case '>':
 	  case '<':
-	    draw_binary_vec4_le(expr, stuff_ok_flag);
+	    draw_binary_vec4_le(expr);
 	    break;
 
 	  case 'l': /* << */
 	  case 'r': /* >> */
 	  case 'R': /* >>> */
-	    draw_binary_vec4_lrs(expr, stuff_ok_flag);
+	    draw_binary_vec4_lrs(expr);
 	    break;
 
 	  case 'o': /* || (logical or) */
@@ -618,7 +618,7 @@ static void draw_binary_vec4(ivl_expr_t expr, int stuff_ok_flag)
       }
 }
 
-static void draw_concat_vec4(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_concat_vec4(ivl_expr_t expr)
 {
 	/* Repeat the concatenation this many times to make a
 	   super-concatenation. */
@@ -631,11 +631,11 @@ static void draw_concat_vec4(ivl_expr_t expr, int stuff_ok_flag)
       assert(num_sube > 0);
 
 	/* Start with the least-significant bits. */
-      draw_eval_vec4(ivl_expr_parm(expr, 0), stuff_ok_flag);
+      draw_eval_vec4(ivl_expr_parm(expr, 0));
 
       for (sub_idx = 1 ; sub_idx < num_sube ; sub_idx += 1) {
 	      /* Concatenate progressively higher parts. */
-	    draw_eval_vec4(ivl_expr_parm(expr, sub_idx), stuff_ok_flag);
+	    draw_eval_vec4(ivl_expr_parm(expr, sub_idx));
 	    fprintf(vvp_out, "    %%concat/vec4;\n");
       }
 
@@ -748,12 +748,12 @@ static void draw_select_vec4(ivl_expr_t expr)
 	    return;
       }
 
-      draw_eval_vec4(subexpr, 0);
-      draw_eval_vec4(base, 0);
+      draw_eval_vec4(subexpr);
+      draw_eval_vec4(base);
       fprintf(vvp_out, "    %%part/%c %u;\n", sign_suff, wid);
 }
 
-static void draw_select_pad_vec4(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_select_pad_vec4(ivl_expr_t expr)
 {
 	// This is the sub-expression to pad/truncate
       ivl_expr_t subexpr = ivl_expr_oper1(expr);
@@ -761,7 +761,7 @@ static void draw_select_pad_vec4(ivl_expr_t expr, int stuff_ok_flag)
       unsigned wid = ivl_expr_width(expr);
 
 	// Push the sub-expression onto the stack.
-      draw_eval_vec4(subexpr, stuff_ok_flag);
+      draw_eval_vec4(subexpr);
 
 	// Special case: The expression is already the correct width,
 	// so there is nothing to be done.
@@ -878,7 +878,7 @@ static void draw_string_vec4(ivl_expr_t expr)
       free(fp);
 }
 
-static void draw_ternary_vec4(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_ternary_vec4(ivl_expr_t expr)
 {
       ivl_expr_t cond = ivl_expr_oper1(expr);
       ivl_expr_t true_ex = ivl_expr_oper2(expr);
@@ -892,7 +892,7 @@ static void draw_ternary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	/* Evaluate the condition expression, including optionally
 	   reducing it to a single bit. Put the result into a flag bit
 	   for use by all the tests. */
-      draw_eval_vec4(cond, STUFF_OK_XZ);
+      draw_eval_vec4(cond);
       if (ivl_expr_width(cond) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
       fprintf(vvp_out, "    %%flag_set/vec4 %d;\n", use_flag);
@@ -902,14 +902,14 @@ static void draw_ternary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	/* If the condition is true or xz (not false), we need the true
 	   expression. If the condition is true, then we ONLY need the
 	   true expression. */
-      draw_eval_vec4(true_ex, stuff_ok_flag);
+      draw_eval_vec4(true_ex);
       fprintf(vvp_out, "    %%jmp/1 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
       fprintf(vvp_out, "T_%u.%u ; End of true expr.\n", thread_count, lab_true);
 
 	/* If the condition is false or xz (not true), we need the false
 	   expression. If the condition is false, then we ONLY need
 	   the false expression. */
-      draw_eval_vec4(false_ex, stuff_ok_flag);
+      draw_eval_vec4(false_ex);
       fprintf(vvp_out, "    %%jmp/0 T_%u.%u, %d;\n", thread_count, lab_out, use_flag);
       fprintf(vvp_out, " ; End of false expr.\n");
 
@@ -945,7 +945,7 @@ static void draw_unary_inc_dec(ivl_expr_t sub, bool incr, bool pre)
 	    break;
       }
 
-      draw_eval_vec4(sub, STUFF_OK_XZ);
+      draw_eval_vec4(sub);
 
       const char*cmd = incr? "%add" : "%sub";
 
@@ -967,45 +967,45 @@ static void draw_unary_inc_dec(ivl_expr_t sub, bool incr, bool pre)
       }
 }
 
-static void draw_unary_vec4(ivl_expr_t expr, int stuff_ok_flag)
+static void draw_unary_vec4(ivl_expr_t expr)
 {
       ivl_expr_t sub = ivl_expr_oper1(expr);
 
       switch (ivl_expr_opcode(expr)) {
 	  case '&':
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%and/r;\n");
 	    break;
 
 	  case '|':
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%or/r;\n");
 	    break;
 
 	  case '^':
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%xor/r;\n");
 	    break;
 
 	  case '~':
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%inv;\n");
 	    break;
 
 	  case '!':
-	    draw_eval_vec4(sub, STUFF_OK_XZ);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%nor/r;\n");
 	    break;
 
 	  case '-':
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%inv;\n");
 	    fprintf(vvp_out, "    %%pushi/vec4 1, 0, %u;\n", ivl_expr_width(sub));
 	    fprintf(vvp_out, "    %%add;\n");
 	    break;
 
 	  case 'A': /* nand (~&) */
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%nand/r;\n");
 	    break;
 
@@ -1026,17 +1026,17 @@ static void draw_unary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	    break;
 
 	  case 'N': /* nor (~|) */
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%nor/r;\n");
 	    break;
 
 	  case 'X': /* xnor (~^) */
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    fprintf(vvp_out, "    %%xnor/r;\n");
 	    break;
 
 	  case 'm': /* abs(m) */
-	    draw_eval_vec4(sub, stuff_ok_flag);
+	    draw_eval_vec4(sub);
 	    if (! ivl_expr_signed(sub))
 		  break;
 
@@ -1062,12 +1062,12 @@ static void draw_unary_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	  case '2': /* Cast expression to bool */
 	    switch (ivl_expr_value(sub)) {
 		case IVL_VT_LOGIC:
-		  draw_eval_vec4(sub, STUFF_OK_XZ);
+		  draw_eval_vec4(sub);
 		  fprintf(vvp_out, "    %%cast2;\n");
 		  resize_vec4_wid(sub, ivl_expr_width(expr));
 		  break;
 		case IVL_VT_BOOL:
-		  draw_eval_vec4(sub, 0);
+		  draw_eval_vec4(sub);
 		  break;
 		case IVL_VT_REAL:
 		  draw_eval_real(sub);
@@ -1085,15 +1085,15 @@ static void draw_unary_vec4(ivl_expr_t expr, int stuff_ok_flag)
       }
 }
 
-void draw_eval_vec4(ivl_expr_t expr, int stuff_ok_flag)
+void draw_eval_vec4(ivl_expr_t expr)
 {
       switch (ivl_expr_type(expr)) {
 	  case IVL_EX_BINARY:
-	    draw_binary_vec4(expr, stuff_ok_flag);
+	    draw_binary_vec4(expr);
 	    return;
 
 	  case IVL_EX_CONCAT:
-	    draw_concat_vec4(expr, stuff_ok_flag);
+	    draw_concat_vec4(expr);
 	    return;
 
 	  case IVL_EX_NUMBER:
@@ -1102,7 +1102,7 @@ void draw_eval_vec4(ivl_expr_t expr, int stuff_ok_flag)
 
 	  case IVL_EX_SELECT:
 	    if (ivl_expr_oper2(expr)==0)
-		  draw_select_pad_vec4(expr, stuff_ok_flag);
+		  draw_select_pad_vec4(expr);
 	    else
 		  draw_select_vec4(expr);
 	    return;
@@ -1120,7 +1120,7 @@ void draw_eval_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	    return;
 
 	  case IVL_EX_TERNARY:
-	    draw_ternary_vec4(expr, stuff_ok_flag);
+	    draw_ternary_vec4(expr);
 	    return;
 
 	  case IVL_EX_UFUNC:
@@ -1128,7 +1128,7 @@ void draw_eval_vec4(ivl_expr_t expr, int stuff_ok_flag)
 	    return;
 
 	  case IVL_EX_UNARY:
-	    draw_unary_vec4(expr, stuff_ok_flag);
+	    draw_unary_vec4(expr);
 	    return;
 
 	  case IVL_EX_PROPERTY:
diff --git a/tgt-vvp/stmt_assign.c b/tgt-vvp/stmt_assign.c
index bae36d09f..927a073c3 100644
--- a/tgt-vvp/stmt_assign.c
+++ b/tgt-vvp/stmt_assign.c
@@ -140,7 +140,7 @@ static void get_vec_from_lval_slice(ivl_lval_t lval, struct vec_slice_info*slice
 	    slice->u_.part_select_dynamic.x_flag = allocate_flag();
 
 	    fprintf(vvp_out, "    %%load/vec4 v%p_%lu;\n", sig, use_word);
-	    draw_eval_vec4(part_off_ex, STUFF_OK_XZ);
+	    draw_eval_vec4(part_off_ex);
 	    fprintf(vvp_out, "    %%flag_mov %u, 4;\n", slice->u_.part_select_dynamic.x_flag);
 	    fprintf(vvp_out, "    %%dup/vec4;\n");
 	    fprintf(vvp_out, "    %%ix/vec4 %u;\n", slice->u_.part_select_dynamic.word_idx_reg);
@@ -661,7 +661,7 @@ static int show_stmt_assign_vector(ivl_statement_t net)
 
       } else {
 	    unsigned wid = ivl_stmt_lwidth(net);
-	    draw_eval_vec4(rval, 0);
+	    draw_eval_vec4(rval);
 	    resize_vec4_wid(rval, wid);
       }
 
@@ -840,7 +840,7 @@ static int show_stmt_assign_sig_string(ivl_statement_t net)
       }
 
       assert(ivl_expr_width(rval)==8);
-      draw_eval_vec4(rval, STUFF_OK_XZ);
+      draw_eval_vec4(rval);
 
 	/* Calculate the character select for the word. */
       int mux_word = allocate_word();
@@ -896,7 +896,7 @@ static int show_stmt_assign_darray_pattern(ivl_statement_t net)
 	    switch (ivl_type_base(element_type)) {
 		case IVL_VT_BOOL:
 		case IVL_VT_LOGIC:
-		  draw_eval_vec4(ivl_expr_parm(rval,idx), STUFF_OK_XZ);
+		  draw_eval_vec4(ivl_expr_parm(rval,idx));
 		  fprintf(vvp_out, "    %%ix/load 3, %u, 0;\n", idx);
 		  fprintf(vvp_out, "    %%store/dar/vec4 v%p_0;\n", var);
 		  break;
@@ -961,7 +961,7 @@ static int show_stmt_assign_sig_darray(ivl_statement_t net)
 	    fprintf(vvp_out, "    %%store/dar/str v%p_0;\n", var);
 
       } else if (mux) {
-	    draw_eval_vec4(rval, STUFF_OK_XZ);
+	    draw_eval_vec4(rval);
 
 	      /* The %store/dar/vec4 expects the array index to be in index
 		 register 3. Calculate the index in place. */
@@ -1028,7 +1028,7 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
 		  assert(ivl_type_packed_dimensions(prop_type) == 1);
 		  assert(ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0));
 
-		  draw_eval_vec4(rval, STUFF_OK_XZ);
+		  draw_eval_vec4(rval);
 		  if (ivl_expr_value(rval)!=IVL_VT_BOOL)
 			fprintf(vvp_out, "    %%cast2;\n");
 
@@ -1041,7 +1041,7 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
 		  assert(ivl_type_packed_dimensions(prop_type) == 1);
 		  assert(ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0));
 
-		  draw_eval_vec4(rval, STUFF_OK_XZ);
+		  draw_eval_vec4(rval);
 
 		  fprintf(vvp_out, "    %%load/obj v%p_0;\n", sig);
 		  fprintf(vvp_out, "    %%store/prop/v %d, %u; Store in logic property %s\n",
diff --git a/tgt-vvp/vvp_priv.h b/tgt-vvp/vvp_priv.h
index 645ff6faf..c2ad0a6b4 100644
--- a/tgt-vvp/vvp_priv.h
+++ b/tgt-vvp/vvp_priv.h
@@ -312,7 +312,7 @@ extern uint64_t get_number_immediate64(ivl_expr_t ex);
  * draw_eval_vec4 evaluates vec4 expressions. The result of the
  * evaluation is the vec4 result in the top of the vec4 expression stack.
  */
-extern void draw_eval_vec4(ivl_expr_t ex, int stuff_ok_flag);
+extern void draw_eval_vec4(ivl_expr_t ex);
 extern void resize_vec4_wid(ivl_expr_t expr, unsigned wid);
 
 /*
diff --git a/tgt-vvp/vvp_process.c b/tgt-vvp/vvp_process.c
index cac3e19a0..ea299c5c9 100644
--- a/tgt-vvp/vvp_process.c
+++ b/tgt-vvp/vvp_process.c
@@ -609,7 +609,7 @@ static int show_stmt_assign_nb(ivl_statement_t net)
 
 	} else {
 	      wid = ivl_stmt_lwidth(net);
-	      draw_eval_vec4(rval, 0);
+	      draw_eval_vec4(rval);
 	      if (ivl_expr_width(rval) != wid) {
 		    if (ivl_expr_signed(rval))
 			  fprintf(vvp_out, "    %%pad/s %u;\n", wid);
@@ -712,7 +712,7 @@ static int show_stmt_case(ivl_statement_t net, ivl_scope_t sscope)
 	/* Evaluate the case condition to the top of the vec4
 	   stack. This expression will be compared multiple times to
 	   each case guard. */
-      draw_eval_vec4(expr,0);
+      draw_eval_vec4(expr);
 
 	/* First draw the branch table.  All the non-default cases
 	   generate a branch out of here, to the code that implements
@@ -731,7 +731,7 @@ static int show_stmt_case(ivl_statement_t net, ivl_scope_t sscope)
 		 instructions below do not completely erase the
 		 value. Do this in fromt of each compare. */
 	    fprintf(vvp_out, "    %%dup/vec4;\n");
-	    draw_eval_vec4(cex, STUFF_OK_RO);
+	    draw_eval_vec4(cex);
 
 	    switch (ivl_statement_type(net)) {
 
@@ -1161,7 +1161,7 @@ static int show_stmt_cassign(ivl_statement_t net)
 
       } else {
 
-	    draw_eval_vec4(rval, STUFF_OK_47);
+	    draw_eval_vec4(rval);
 	    resize_vec4_wid(rval, ivl_stmt_lwidth(net));
 
 	      /* Write out initial continuous assign instructions to assign
@@ -1258,7 +1258,7 @@ static int show_stmt_condit(ivl_statement_t net, ivl_scope_t sscope)
 
       show_stmt_file_line(net, "If statement.");
 
-      draw_eval_vec4(expr, STUFF_OK_XZ|STUFF_OK_47|STUFF_OK_RO);
+      draw_eval_vec4(expr);
 
       lab_false = local_count++;
       lab_out = local_count++;
@@ -1339,7 +1339,7 @@ static int show_stmt_delayx(ivl_statement_t net, ivl_scope_t sscope)
 
 	  case IVL_VT_BOOL:
 	  case IVL_VT_LOGIC: {
-		draw_eval_vec4(expr, 0);
+		draw_eval_vec4(expr);
 		fprintf(vvp_out, "    %%ix/vec4 %d;\n", use_idx);
 		break;
 	  }
@@ -1404,7 +1404,7 @@ static int show_stmt_do_while(ivl_statement_t net, ivl_scope_t sscope)
 	/* Draw the evaluation of the condition expression, and test
 	   the result. If the expression evaluates to true, then
 	   branch to the top label. */
-      draw_eval_vec4(ivl_stmt_cond_expr(net), STUFF_OK_XZ|STUFF_OK_47);
+      draw_eval_vec4(ivl_stmt_cond_expr(net));
       if (ivl_expr_width(ivl_stmt_cond_expr(net)) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
@@ -1435,7 +1435,7 @@ static int show_stmt_force(ivl_statement_t net)
 
       } else {
 
-            draw_eval_vec4(rval, STUFF_OK_47);
+            draw_eval_vec4(rval);
 
               /* Write out initial continuous assign instructions to assign
                  the expression value to the l-value. */
@@ -1651,7 +1651,7 @@ static int show_stmt_repeat(ivl_statement_t net, ivl_scope_t sscope)
       show_stmt_file_line(net, "Repeat statement.");
 
 	/* Calculate the repeat count onto the top of the vec4 stack. */
-      draw_eval_vec4(expr, STUFF_OK_XZ);
+      draw_eval_vec4(expr);
 
 	/* Test that 0 < expr, escape if expr <= 0. If the expr is
 	   unsigned, then we only need to try to escape if expr==0 as
@@ -1758,7 +1758,7 @@ static int show_stmt_while(ivl_statement_t net, ivl_scope_t sscope)
 	/* Draw the evaluation of the condition expression, and test
 	   the result. If the expression evaluates to false, then
 	   branch to the out label. */
-      draw_eval_vec4(ivl_stmt_cond_expr(net), STUFF_OK_XZ|STUFF_OK_47);
+      draw_eval_vec4(ivl_stmt_cond_expr(net));
       if (ivl_expr_width(ivl_stmt_cond_expr(net)) > 1) {
 	    fprintf(vvp_out, "    %%or/r;\n");
       }
@@ -1833,7 +1833,7 @@ static int show_push_frontback_method(ivl_statement_t net)
 	    fprintf(vvp_out, "    %%store/%s/str v%p_0;\n", type_code, var);
 	    break;
 	  default:
-	    draw_eval_vec4(parm1, STUFF_OK_XZ);
+	    draw_eval_vec4(parm1);
 	    fprintf(vvp_out, "    %%store/%s/v v%p_0, %u;\n",
 		    type_code, var, width_of_packed_type(element_type));
 	    break;