diff --git a/vvp/codes.h b/vvp/codes.h
index 7dcd43021..166fb2d76 100644
--- a/vvp/codes.h
+++ b/vvp/codes.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: codes.h,v 1.52 2002/11/07 02:32:39 steve Exp $"
+#ident "$Id: codes.h,v 1.53 2002/11/08 04:59:57 steve Exp $"
 #endif
 
 
@@ -42,6 +42,7 @@ extern bool of_ANDR(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_D(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_MEM(vthread_t thr, vvp_code_t code);
+extern bool of_ASSIGN_V0(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_X0(vthread_t thr, vvp_code_t code);
 extern bool of_BLEND(vthread_t thr, vvp_code_t code);
 extern bool of_BREAKPOINT(vthread_t thr, vvp_code_t code);
@@ -159,6 +160,9 @@ extern vvp_code_t codespace_index(vvp_cpoint_t ptr);
 
 /*
  * $Log: codes.h,v $
+ * Revision 1.53  2002/11/08 04:59:57  steve
+ *  Add the %assign/v0 instruction.
+ *
  * Revision 1.52  2002/11/07 02:32:39  steve
  *  Add vector set and load instructions.
  *
diff --git a/vvp/compile.cc b/vvp/compile.cc
index 2379bc376..ae28d13f0 100644
--- a/vvp/compile.cc
+++ b/vvp/compile.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compile.cc,v 1.144 2002/11/07 02:32:39 steve Exp $"
+#ident "$Id: compile.cc,v 1.145 2002/11/08 04:59:58 steve Exp $"
 #endif
 
 # include  "arith.h"
@@ -87,8 +87,9 @@ const static struct opcode_table_s opcode_table[] = {
       { "%and",    of_AND,    3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%and/r",  of_ANDR,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%assign", of_ASSIGN, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
-      { "%assign/d", of_ASSIGN_D, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
+      { "%assign/d", of_ASSIGN_D, 3,  {OA_FUNC_PTR, OA_BIT1, OA_BIT2} },
       { "%assign/m",of_ASSIGN_MEM,3,{OA_MEM_PTR,OA_BIT1,     OA_BIT2} },
+      { "%assign/v0",of_ASSIGN_V0,3,{OA_FUNC_PTR,OA_BIT1,    OA_BIT2} },
       { "%assign/x0",of_ASSIGN_X0,3,{OA_FUNC_PTR,OA_BIT1,    OA_BIT2} },
       { "%blend",  of_BLEND,  3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%breakpoint", of_BREAKPOINT, 0,  {OA_NONE, OA_NONE, OA_NONE} },
@@ -1482,6 +1483,9 @@ void compile_net(char*label, char*name, int msb, int lsb, bool signed_flag,
 
 /*
  * $Log: compile.cc,v $
+ * Revision 1.145  2002/11/08 04:59:58  steve
+ *  Add the %assign/v0 instruction.
+ *
  * Revision 1.144  2002/11/07 02:32:39  steve
  *  Add vector set and load instructions.
  *
diff --git a/vvp/opcodes.txt b/vvp/opcodes.txt
index aa64177c3..8c767dbb0 100644
--- a/vvp/opcodes.txt
+++ b/vvp/opcodes.txt
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
  *
- *  $Id: opcodes.txt,v 1.43 2002/11/07 02:32:39 steve Exp $
+ *  $Id: opcodes.txt,v 1.44 2002/11/08 04:59:58 steve Exp $
  */
 
 
@@ -49,6 +49,7 @@ means the following:
 
 * %assign <var-label>, <delay>, <bit>
 * %assign/d <var-label>, <delay>, <bit>
+* %assign/v0 <var-label>, <delay>, <bit>
 
 This does a non-blocking assignment to a variable. The <label>
 identifies the affected variable, and the <delay> gives the delay when
@@ -60,6 +61,8 @@ The %assign/d instruction is exactly the same as the %assign
 instruction, except that the <delay> specifies one of the index
 registers, that contain a calculated delay.
 
+The %assign/v0 instruction is a vector version of %assign, with the
+vector width in index register 0.
 
 * %assign/m <memory-label>, <delay>, <bit>
 
diff --git a/vvp/vthread.cc b/vvp/vthread.cc
index 53c247985..8569e758a 100644
--- a/vvp/vthread.cc
+++ b/vvp/vthread.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: vthread.cc,v 1.92 2002/11/07 03:11:43 steve Exp $"
+#ident "$Id: vthread.cc,v 1.93 2002/11/08 04:59:58 steve Exp $"
 #endif
 
 # include  "vthread.h"
@@ -487,6 +487,32 @@ bool of_ASSIGN_D(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
+/*
+ * This is %assign/v0 <label>, <delay>, <bit>
+ * Index register 0 contains a vector width.
+ */
+bool of_ASSIGN_V0(vthread_t thr, vvp_code_t cp)
+{
+      unsigned wid = thr->index[0];
+      assert(wid > 0);
+      assert(wid < 0x10000);
+
+      unsigned delay = cp->bit_idx[0];
+      unsigned bit = cp->bit_idx[1];
+
+      for (unsigned idx = 0 ;  idx < wid ;  idx += 1) {
+	    vvp_ipoint_t iptr = ipoint_index(cp->iptr, idx);
+
+	    unsigned char bit_val = thr_get_bit(thr, bit);
+	    schedule_assign(iptr, bit_val, delay);
+
+	    if (bit >= 4)
+		  bit += 1;
+      }
+
+      return true;
+}
+
 bool of_ASSIGN_X0(vthread_t thr, vvp_code_t cp)
 {
       unsigned char bit_val = thr_get_bit(thr, cp->bit_idx[1]);
@@ -2466,6 +2492,9 @@ bool of_CALL_UFUNC(vthread_t thr, vvp_code_t cp)
 
 /*
  * $Log: vthread.cc,v $
+ * Revision 1.93  2002/11/08 04:59:58  steve
+ *  Add the %assign/v0 instruction.
+ *
  * Revision 1.92  2002/11/07 03:11:43  steve
  *  functor_set takes bit and strength, not 2 strengths.
  *