From 1b551aaf94439e2512f442488bab7468495355e2 Mon Sep 17 00:00:00 2001 From: steve Date: Fri, 23 Mar 2007 23:26:51 +0000 Subject: [PATCH] Update to v0.8.4 release. --- Makefile.in | 4 ++-- verilog.spec | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile.in b/Makefile.in index f1b15d819..6226b3316 100644 --- a/Makefile.in +++ b/Makefile.in @@ -16,7 +16,7 @@ # 59 Temple Place - Suite 330 # Boston, MA 02111-1307, USA # -#ident "$Id: Makefile.in,v 1.169.2.5 2006/10/04 17:08:59 steve Exp $" +#ident "$Id: Makefile.in,v 1.169.2.6 2007/03/23 23:26:51 steve Exp $" # # SHELL = /bin/sh @@ -25,7 +25,7 @@ SHELL = /bin/sh # by the compiler. It reflects the assigned version number for the # product as a whole. Most components also print the CVS Name: token # in order to get a more automatic version stamp as well. -VERSION = 0.8.3 +VERSION = 0.8.4 prefix = @prefix@ exec_prefix = @exec_prefix@ diff --git a/verilog.spec b/verilog.spec index 8dd6a86a1..fd23df8fb 100644 --- a/verilog.spec +++ b/verilog.spec @@ -1,10 +1,10 @@ Summary: Icarus Verilog Name: verilog -Version: 0.8.3 +Version: 0.8.4 Release: 0 License: GPL Group: Applications/Engineering -Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.3.tar.gz +Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz URL: http://www.icarus.com/eda/verilog/index.html Packager: Stephen Williams @@ -29,7 +29,7 @@ engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. %prep -%setup -n verilog-0.8.3 +%setup -n verilog-0.8.4 %build %ifarch x86_64