diff --git a/ieee1364-notes.txt b/ieee1364-notes.txt
index b2dd2b847..a91a52966 100644
--- a/ieee1364-notes.txt
+++ b/ieee1364-notes.txt
@@ -140,8 +140,32 @@ integers is unspecified. This, by the way, also applies to module
 ports.
 
 
-$Id: ieee1364-notes.txt,v 1.2 2000/11/19 22:03:04 steve Exp $
+* ROUNDING OF TIME
+
+When the `timescale directive is present, the compiler is supposed to
+round fractional times (after scaling) to the nearest integer. The
+confusing bit here is that it is apparently conventional that if the
+`timescale directive is *not* present, times are rounded towards zero
+always.
+
+
+* VALUE OF X IN PRIMITIVE OUTPUTS
+
+The IEEE1364-1995 standard clearly states in Table 8-1 that the x
+symbols is allowed in input columns, but is not allowed in
+outputs. Furthermore, none of the examples have an x in the output of
+a primitive. Table 8-1 in the IEEE1364-2000 also says the same thing.
+
+However, the BNF clearly states that 0, 1, x and X are valid
+output_symbol characters. The standard is self contradictory. So I
+take it that x is allowed, as that is what Verilog-XL does.
+
+
+$Id: ieee1364-notes.txt,v 1.3 2000/12/15 00:21:46 steve Exp $
 $Log: ieee1364-notes.txt,v $
+Revision 1.3  2000/12/15 00:21:46  steve
+ rounding of time and x in primitives.
+
 Revision 1.2  2000/11/19 22:03:04  steve
  Integer parameter comments.