From 0c883a00bf7292851b2d6320e157891c2152a769 Mon Sep 17 00:00:00 2001
From: Nick Gasson <nick@nickg.me.uk>
Date: Tue, 24 Aug 2010 22:17:11 +0100
Subject: [PATCH] Change VHDL $finish to use report not assert

Changes:

   assert false report "SIMULATION FINISHED" severity failure;

To just:

   report "SIMULATION FINISHED" severity failure;
---
 tgt-vhdl/stmt.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index bc1abdeed..1fcc44fae 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -54,7 +54,9 @@ static int draw_stask_finish(vhdl_procedural *proc, stmt_container *container,
       container->add_stmt(new vhdl_pcall_stmt("work.Verilog_Support.Finish"));
    }
    else {
-      container->add_stmt(new vhdl_assert_stmt("SIMULATION FINISHED"));
+      container->add_stmt(
+         new vhdl_report_stmt(new vhdl_const_string("SIMULATION FINISHED"),
+                              SEVERITY_FAILURE));
    }
    
    return 0;