From 095e6daa0ae6e1f7b14c56a40fc7062de80f1b09 Mon Sep 17 00:00:00 2001 From: Cary R Date: Sun, 9 Jul 2023 05:00:54 -0700 Subject: [PATCH] Cannot use posedge, negedge or edge with a real expression --- elaborate.cc | 25 ++++++++++++++++++++++++- ivtest/gold/real_edges.gold | 4 ++++ ivtest/ivltests/real_edges.v | 13 +++++++++++++ ivtest/regress-sv.list | 1 + 4 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 ivtest/gold/real_edges.gold create mode 100644 ivtest/ivltests/real_edges.v diff --git a/elaborate.cc b/elaborate.cc index 0ee0656c4..9f854c2dd 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 1998-2022 Stephen Williams (steve@icarus.com) + * Copyright (c) 1998-2023 Stephen Williams (steve@icarus.com) * Copyright CERN 2013 / Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it @@ -4886,6 +4886,29 @@ cerr << endl; continue; } + // posedge, negedge and edge are not allowed on real expressions. + if ((tmp->expr_type() == IVL_VT_REAL) && + (expr_[idx]->type() != PEEvent::ANYEDGE)) { + cerr << get_fileline() << ": error: '"; + switch (expr_[idx]->type()) { + case PEEvent::POSEDGE: + cerr << "posedge"; + break; + case PEEvent::NEGEDGE: + cerr << "negedge"; + break; + case PEEvent::EDGE: + cerr << "edge"; + break; + default: + ivl_assert(*this, 0); + } + cerr << "' cannot be used with real expressions '" + << *expr_[idx]->expr() << "'." << endl; + des->errors += 1; + continue; + } + NetNet*expr = tmp->synthesize(des, scope, tmp); if (expr == 0) { expr_[idx]->dump(cerr); diff --git a/ivtest/gold/real_edges.gold b/ivtest/gold/real_edges.gold new file mode 100644 index 000000000..18104682f --- /dev/null +++ b/ivtest/gold/real_edges.gold @@ -0,0 +1,4 @@ +./ivltests/real_edges.v:5: error: 'posedge' cannot be used with real expressions 'rval'. +./ivltests/real_edges.v:6: error: 'negedge' cannot be used with real expressions 'rval'. +./ivltests/real_edges.v:7: error: 'edge' cannot be used with real expressions 'rval'. +3 error(s) during elaboration. diff --git a/ivtest/ivltests/real_edges.v b/ivtest/ivltests/real_edges.v new file mode 100644 index 000000000..a33f1d35c --- /dev/null +++ b/ivtest/ivltests/real_edges.v @@ -0,0 +1,13 @@ +module top; + real rval; + + always @(rval) $display("any change"); + always @(posedge rval) $display("posedge"); + always @(negedge rval) $display("negedge"); + always @(edge rval) $display("edge"); + + initial begin + #1 rval = 1.0; + #1 rval = 0.0; + end +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index 362535b78..813e2647a 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -996,3 +996,4 @@ br_gh840a CE,-g2012 ivltests br_gh840b CE,-g2012 ivltests bitsel_real_idx CE,-g2012 ivltests gold=bitsel_real_idx.gold partsel_real_idx CE,-g2012 ivltests gold=partsel_real_idx.gold +real_edges CE,-g2012 ivltests gold=real_edges.gold