From d0408040367250e1d659b4118d45b2cdb6d72f7d Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 12 Jun 2023 08:59:17 -0700 Subject: [PATCH 1/4] parser: Fix line location for implicit named port connections The implicitly generated identifier for implicit named port connections gets its file and line information from the optional attributes. If no attribute list is specified this will just point to the beginning of the file resulting in incorrect line information. Use the file and line information from the identifier token instead to fix this. Signed-off-by: Lars-Peter Clausen --- parse.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/parse.y b/parse.y index d997c858e..8c548476c 100644 --- a/parse.y +++ b/parse.y @@ -5731,7 +5731,7 @@ port_name { named_pexpr_t*tmp = new named_pexpr_t; tmp->name = lex_strings.make($3); tmp->parm = new PEIdent(lex_strings.make($3), true); - FILE_NAME(tmp->parm, @1); + FILE_NAME(tmp->parm, @3); delete[]$3; delete $1; $$ = tmp; From ee4476fed2ada40b6c3572c3da667a1b8ce2bcd9 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 12 Jun 2023 20:31:11 -0700 Subject: [PATCH 2/4] parser: Require SystemVerilog for implicit named port connections Implicit named port connections are only supported by SystemVerilog. Add a check to generate an error when trying to use it in Verilog mode. Regression test br_gh315 is modified to run in SystemVerilog mode since it makes use of implicit named port connections. Signed-off-by: Lars-Peter Clausen --- ivtest/regress-vlg.list | 2 +- parse.y | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 862fcbc63..858dc4bc9 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -325,7 +325,7 @@ br_gh283a normal ivltests br_gh283b normal ivltests br_gh283c normal ivltests br_gh309 normal ivltests -br_gh315 normal,-gspecify ivltests +br_gh315 normal,-g2005-sv,-gspecify ivltests br_gh316a normal,-gspecify ivltests br_gh316b normal,-gspecify ivltests br_gh316c normal,-gspecify ivltests diff --git a/parse.y b/parse.y index 8c548476c..5c98f4fb1 100644 --- a/parse.y +++ b/parse.y @@ -5728,7 +5728,8 @@ port_name $$ = tmp; } | attribute_list_opt '.' IDENTIFIER - { named_pexpr_t*tmp = new named_pexpr_t; + { pform_requires_sv(@3, "Implicit named port connections"); + named_pexpr_t*tmp = new named_pexpr_t; tmp->name = lex_strings.make($3); tmp->parm = new PEIdent(lex_strings.make($3), true); FILE_NAME(tmp->parm, @3); From cc74c7f33297fb70fc14ba1709cb6ca25cadce8f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 13 Jun 2023 19:25:52 -0700 Subject: [PATCH 3/4] vvp_reg.py: Add support for gold files for CE tests Some tests require a specific compiler error, rather than just failing. Add support for this by allowing to check for gold files for CE tests. Signed-off-by: Lars-Peter Clausen --- ivtest/run_ivl.py | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/ivtest/run_ivl.py b/ivtest/run_ivl.py index c81e72d9b..dc3df3f48 100644 --- a/ivtest/run_ivl.py +++ b/ivtest/run_ivl.py @@ -114,6 +114,15 @@ def run_cmd(cmd: list) -> subprocess.CompletedProcess: res = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE) return res +def check_gold(it_key : str, it_gold : str, log_list : list) -> bool: + compared = True + for log_name in log_list: + log_path = os.path.join("log", "{key}-{log}.log".format(key=it_key, log=log_name)) + gold_path = os.path.join("gold", "{gold}-{log}.gold".format(gold=it_gold, log=log_name)) + compared = compared and compare_files(log_path, gold_path) + + return compared + def run_CE(options : dict) -> list: ''' Run the compiler, and expect an error @@ -123,6 +132,7 @@ def run_CE(options : dict) -> list: it_key = options['key'] it_dir = options['directory'] it_args = options['iverilog_args'] + it_gold = options['gold'] build_runtime(it_key) @@ -130,10 +140,14 @@ def run_CE(options : dict) -> list: res = run_cmd(cmd) log_results(it_key, "iverilog", res) + log_list = ["iverilog-stdout", "iverilog-stderr"] + if res.returncode == 0: return [1, "Failed - CE (no error reported)"] elif res.returncode >= 256: return [1, "Failed - CE (execution error)"] + elif it_gold is not None and not check_gold(it_key, it_gold, log_list): + return [1, "Failed - CE (Gold output doesn't match actual output.)"] else: return [0, "Passed - CE"] @@ -150,11 +164,7 @@ def check_run_outputs(options : dict, expected_fail : bool, it_stdout : str, log it_diff = options['diff'] if it_gold is not None: - compared = True - for log_name in log_list: - log_path = os.path.join("log", "{key}-{log}.log".format(key=it_key, log=log_name)) - gold_path = os.path.join("gold", "{gold}-{log}.gold".format(gold=it_gold, log=log_name)) - compared = compared and compare_files(log_path, gold_path) + compared = check_gold(it_key, it_gold, log_list) if expected_fail: if compared: From 9357a62dce35ebf769f23e94666c1f69132412a0 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 13 Jun 2023 19:24:30 -0700 Subject: [PATCH 4/4] Add regression test for implicit named port connection errors Check that the file and line location is correct for errors related to implicit named port connections. Signed-off-by: Lars-Peter Clausen --- ivtest/gold/br_gh939-iverilog-stderr.gold | 4 ++++ ivtest/ivltests/br_gh939.v | 11 +++++++++++ ivtest/regress-vvp.list | 1 + ivtest/vvp_tests/br_gh939.json | 6 ++++++ 4 files changed, 22 insertions(+) create mode 100644 ivtest/gold/br_gh939-iverilog-stderr.gold create mode 100644 ivtest/ivltests/br_gh939.v create mode 100644 ivtest/vvp_tests/br_gh939.json diff --git a/ivtest/gold/br_gh939-iverilog-stderr.gold b/ivtest/gold/br_gh939-iverilog-stderr.gold new file mode 100644 index 000000000..e7388707a --- /dev/null +++ b/ivtest/gold/br_gh939-iverilog-stderr.gold @@ -0,0 +1,4 @@ +ivltests/br_gh939.v:10: error: Net o is not defined in this context. +ivltests/br_gh939.v:10: error: Output port expression must support continuous assignment. +ivltests/br_gh939.v:10: : Port 1 (o) of M is connected to o +2 error(s) during elaboration. diff --git a/ivtest/ivltests/br_gh939.v b/ivtest/ivltests/br_gh939.v new file mode 100644 index 000000000..99ace6cac --- /dev/null +++ b/ivtest/ivltests/br_gh939.v @@ -0,0 +1,11 @@ +// Check the line and file information for errors related to implicit named port +// connections are correct. + +module M( + output o +); +endmodule + +module test; + M i_m(.o); // Error, no net named o +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index f999793ac..da56a85bf 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -5,6 +5,7 @@ array_packed_write_read vvp_tests/array_packed_write_read.json br_gh13a vvp_tests/br_gh13a.json br_gh13a-vlog95 vvp_tests/br_gh13a-vlog95.json +br_gh939 vvp_tests/br_gh939.json case1 vvp_tests/case1.json case2 vvp_tests/case2.json case2-S vvp_tests/case2-S.json diff --git a/ivtest/vvp_tests/br_gh939.json b/ivtest/vvp_tests/br_gh939.json new file mode 100644 index 000000000..4a8d250e3 --- /dev/null +++ b/ivtest/vvp_tests/br_gh939.json @@ -0,0 +1,6 @@ +{ + "type" : "CE", + "source" : "br_gh939.v", + "gold" : "br_gh939", + "iverilog-args" : [ "-g2005-sv" ] +}