From 06111357581dcfa7bf3a1bffc756712fb1dca2ba Mon Sep 17 00:00:00 2001 From: Cary R Date: Sun, 29 Jun 2014 20:38:23 -0700 Subject: [PATCH] Some more cppcheck cleanup/updates --- Makefile.in | 2 ++ cppcheck.sup | 4 ++-- design_dump.cc | 5 ++--- driver/Makefile.in | 6 +++++- driver/cfparse.y | 2 +- elab_net.cc | 4 ++-- elaborate.cc | 1 - parse.y | 2 +- pform.cc | 8 ++++---- pform_dump.cc | 4 ++-- pform_pclass.cc | 4 ++-- tgt-pcb/Makefile.in | 2 +- tgt-stub/Makefile.in | 3 ++- tgt-stub/cppcheck.sup | 8 ++++++++ tgt-verilog/Makefile.in | 3 ++- tgt-verilog/cppcheck.sup | 5 +++++ tgt-verilog/verilog.c | 4 ++-- tgt-vhdl/Makefile.in | 3 ++- tgt-vhdl/cppcheck.sup | 8 ++++++++ tgt-vhdl/logic.cc | 5 ++--- tgt-vhdl/scope.cc | 16 ++++++++-------- vhdlpp/Makefile.in | 6 +++++- vhdlpp/scope.cc | 6 ++---- vvp/Makefile.in | 3 +++ vvp/delay.cc | 4 ++-- vvp/event.cc | 5 ++--- vvp/logic.cc | 4 ++-- vvp/part.cc | 4 ++-- vvp/vpi_tasks.cc | 4 ++-- vvp/vvp_net.cc | 2 +- vvp/vvp_net_sig.cc | 8 ++++---- 31 files changed, 88 insertions(+), 57 deletions(-) create mode 100644 tgt-stub/cppcheck.sup create mode 100644 tgt-verilog/cppcheck.sup create mode 100644 tgt-vhdl/cppcheck.sup diff --git a/Makefile.in b/Makefile.in index c31e2d735..846462440 100644 --- a/Makefile.in +++ b/Makefile.in @@ -175,6 +175,8 @@ endif cppcheck: $(O:.o=.cc) $(srcdir)/dosify.c $(srcdir)/version.c cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ + -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \ + -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \ --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ cppcheck-all: diff --git a/cppcheck.sup b/cppcheck.sup index 839dd525a..9d2cbc034 100644 --- a/cppcheck.sup +++ b/cppcheck.sup @@ -1,3 +1,3 @@ // These are correct and are used to find the base (zero) pin. -thisSubtraction:netlist.h:4589 -thisSubtraction:netlist.h:4598 +thisSubtraction:netlist.h:4863 +thisSubtraction:netlist.h:4872 diff --git a/design_dump.cc b/design_dump.cc index 65f602f3c..102c252a4 100644 --- a/design_dump.cc +++ b/design_dump.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 1998-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -218,8 +218,7 @@ static inline void dump_scope_path(ostream&o, const NetScope*scope) dump_scope_path(o, parent); o << "."; } - const hname_t name = scope->fullname(); - o << name; + o << scope->fullname(); } ostream& operator <<(ostream&o, struct __ScopePathManip marg) diff --git a/driver/Makefile.in b/driver/Makefile.in index a94001e30..a5b5c4cdf 100644 --- a/driver/Makefile.in +++ b/driver/Makefile.in @@ -67,7 +67,11 @@ distclean: clean rm -f Makefile config.log cppcheck: $(O:.o=.c) - cppcheck --enable=all -f $(INCLUDE_PATH) $^ + cppcheck --enable=all -f \ + -UYY_USER_INIT \ + -UYYPARSE_PARAM -UYYPRINT -Ushort -Uyyoverflow \ + -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \ + $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in ../config.status cd ..; ./config.status --file=driver/$@ diff --git a/driver/cfparse.y b/driver/cfparse.y index 13fcb85c9..493694ead 100644 --- a/driver/cfparse.y +++ b/driver/cfparse.y @@ -221,7 +221,7 @@ item } | error - { fprintf(stderr, "Error: unable to parse line %d in " + { fprintf(stderr, "Error: unable to parse line %u in " "%s.\n", cflloc.first_line, current_file); return 1; } diff --git a/elab_net.cc b/elab_net.cc index cbaf15202..09a38f454 100644 --- a/elab_net.cc +++ b/elab_net.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 1999-2012 Stephen Williams (steve@icarus.com) + * Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com) * Copyright CERN 2012 / Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it @@ -595,7 +595,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, midx = lidx + tmp_wid - 1; } - } else if (gn_system_verilog() && sig->unpacked_dimensions() > 0 && path_tail.index.size() == 0) { + } else if (gn_system_verilog() && sig->unpacked_dimensions() > 0 && path_tail.index.empty()) { // In this case, we are doing a continuous assignment to // an unpacked array. The NetNet representation is a diff --git a/elaborate.cc b/elaborate.cc index 783840a81..43e97afea 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -3187,7 +3187,6 @@ NetProc* PChainConstructor::elaborate(Design*des, NetScope*scope) const NetBlock*tmp = new NetBlock(NetBlock::SEQU, 0); tmp->set_line(*this); return tmp; - return 0; } NetProc* PCondit::elaborate(Design*des, NetScope*scope) const diff --git a/parse.y b/parse.y index 94de008a8..dbbb2d799 100644 --- a/parse.y +++ b/parse.y @@ -170,7 +170,7 @@ template void append(vector&out, const vector&in) */ static void strip_tail_items(list*lst) { - while (lst->size() > 0) { + while (! lst->empty()) { if (lst->back() != 0) return; lst->pop_back(); diff --git a/pform.cc b/pform.cc index 7b899b688..ff4114ba0 100644 --- a/pform.cc +++ b/pform.cc @@ -1534,7 +1534,7 @@ void pform_make_udp(perm_string name, list*parms, unsigned idx; for (cur = parms->begin(), idx = 0 ; cur != parms->end() - ; idx++, cur++) { + ; ++ idx, ++ cur) { pins[idx] = defs[*cur]; pin_names[idx] = *cur; } @@ -1700,7 +1700,7 @@ void pform_make_udp(perm_string name, bool synchronous_flag, unsigned idx; for (cur = parms->begin(), idx = 1 ; cur != parms->end() - ; idx += 1, cur++) { + ; idx += 1, ++ cur) { assert(idx < pins.count()); pins[idx] = new PWire(*cur, NetNet::WIRE, NetNet::PINPUT, IVL_VT_LOGIC); @@ -2912,13 +2912,13 @@ extern PSpecPath* pform_make_specify_path(const struct vlltype&li, list::const_iterator cur; idx = 0; - for (idx = 0, cur = src->begin() ; cur != src->end() ; idx++, cur++) { + for (idx = 0, cur = src->begin() ; cur != src->end() ; ++ idx, ++ cur) { path->src[idx] = *cur; } assert(idx == path->src.size()); delete src; - for (idx = 0, cur = dst->begin() ; cur != dst->end() ; idx++, cur++) { + for (idx = 0, cur = dst->begin() ; cur != dst->end() ; ++ idx, ++ cur) { path->dst[idx] = *cur; } assert(idx == path->dst.size()); diff --git a/pform_dump.cc b/pform_dump.cc index 65fcdbfe4..5cda43ba1 100644 --- a/pform_dump.cc +++ b/pform_dump.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 1998-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -196,7 +196,7 @@ void class_type_t::pform_dump(ostream&out, unsigned indent) const out << setw(indent) << "" << "class " << name; if (base_type) out << " extends "; - if (base_args.size() > 0) { + if (! base_args.empty()) { out << " ("; for (list::const_iterator cur = base_args.begin() ; cur != base_args.end() ; ++cur) { diff --git a/pform_pclass.cc b/pform_pclass.cc index 3b7b94d59..0636126f4 100644 --- a/pform_pclass.cc +++ b/pform_pclass.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 2012-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -46,7 +46,7 @@ void pform_start_class_declaration(const struct vlltype&loc, class_type_t*type, assert(type->base_type == 0); type->base_type = base_type; - assert(type->base_args.size() == 0); + assert(type->base_args.empty()); if (base_exprs) { for (list::iterator cur = base_exprs->begin() ; cur != base_exprs->end() ; ++ cur) { diff --git a/tgt-pcb/Makefile.in b/tgt-pcb/Makefile.in index a7521775b..dd73e27ea 100644 --- a/tgt-pcb/Makefile.in +++ b/tgt-pcb/Makefile.in @@ -63,7 +63,7 @@ distclean: clean cppcheck: $(O:.o=.cc) cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ -UYY_USER_INIT \ - -UYYPARSE_PARAM -UYYPRINT -Usize_t -Ushort -Uyyoverflow \ + -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \ -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \ --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ diff --git a/tgt-stub/Makefile.in b/tgt-stub/Makefile.in index b294d3000..874cbc3bf 100644 --- a/tgt-stub/Makefile.in +++ b/tgt-stub/Makefile.in @@ -57,7 +57,8 @@ distclean: clean rm -f Makefile config.log cppcheck: $(O:.o=.c) - cppcheck --enable=all -f $(INCLUDE_PATH) $^ + cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ + --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in ../config.status cd ..; ./config.status --file=tgt-stub/$@ diff --git a/tgt-stub/cppcheck.sup b/tgt-stub/cppcheck.sup new file mode 100644 index 000000000..c93fc277a --- /dev/null +++ b/tgt-stub/cppcheck.sup @@ -0,0 +1,8 @@ +// These are the global access functions called from the compiler so they +// are not used here. + +// target_design() +unusedFunction:stub.c:1731 + +// target_query() +unusedFunction:stub.c:1795 diff --git a/tgt-verilog/Makefile.in b/tgt-verilog/Makefile.in index 3fdcb205e..2c7ebc3e1 100644 --- a/tgt-verilog/Makefile.in +++ b/tgt-verilog/Makefile.in @@ -55,7 +55,8 @@ distclean: clean rm -f Makefile config.log cppcheck: $(O:.o=.c) - cppcheck --enable=all -f $(INCLUDE_PATH) $^ + cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ + --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in ../config.status cd ..; ./config.status --file=tgt-verilog/$@ diff --git a/tgt-verilog/cppcheck.sup b/tgt-verilog/cppcheck.sup new file mode 100644 index 000000000..f10e95e54 --- /dev/null +++ b/tgt-verilog/cppcheck.sup @@ -0,0 +1,5 @@ +// These are the global access functions called from the compiler so they +// are not used here. + +// target_design() +unusedFunction:verilog.c:408 diff --git a/tgt-verilog/verilog.c b/tgt-verilog/verilog.c index d9c6af93f..333277a59 100644 --- a/tgt-verilog/verilog.c +++ b/tgt-verilog/verilog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -232,7 +232,6 @@ static void show_expression(ivl_expr_t net) static void show_assign_lval(ivl_lval_t lval) { ivl_nexus_t nex; - ivl_nexus_ptr_t ptr; ivl_signal_t sig=NULL; unsigned idx; @@ -245,6 +244,7 @@ static void show_assign_lval(ivl_lval_t lval) for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) { unsigned pin; + ivl_nexus_ptr_t ptr; ptr = ivl_nexus_ptr(nex, idx); sig = ivl_nexus_ptr_sig(ptr); diff --git a/tgt-vhdl/Makefile.in b/tgt-vhdl/Makefile.in index 5c1daf11e..b86c11a98 100644 --- a/tgt-vhdl/Makefile.in +++ b/tgt-vhdl/Makefile.in @@ -60,7 +60,8 @@ distclean: clean rm -f stamp-vhdl_config-h vhdl_config.h cppcheck: $(O:.o=.cc) - cppcheck --enable=all -f $(INCLUDE_PATH) $^ + cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ + --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in ../config.status cd ..; ./config.status --file=tgt-vhdl/$@ diff --git a/tgt-vhdl/cppcheck.sup b/tgt-vhdl/cppcheck.sup new file mode 100644 index 000000000..37a3b956f --- /dev/null +++ b/tgt-vhdl/cppcheck.sup @@ -0,0 +1,8 @@ +// These are the global access functions called from the compiler so they +// are not used here. + +// target_design() +unusedFunction:vhdl.cc:96 + +// target_query() +unusedFunction:vhdl.cc:137 diff --git a/tgt-vhdl/logic.cc b/tgt-vhdl/logic.cc index f6d03c373..098d4a9fe 100644 --- a/tgt-vhdl/logic.cc +++ b/tgt-vhdl/logic.cc @@ -1,7 +1,7 @@ /* * VHDL code generation for logic devices. * - * Copyright (C) 2008-2011 Nick Gasson (nick@nickg.me.uk) + * Copyright (C) 2008-2014 Nick Gasson (nick@nickg.me.uk) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -117,8 +117,7 @@ static void comb_udp_logic(vhdl_arch *arch, ivl_net_logic_t log) ss << ivl_logic_basename(log) << "_Tmp"; int msb = ivl_udp_nin(udp) - 1; vhdl_type *tmp_type = vhdl_type::std_logic_vector(msb, 0); - vhdl_signal_decl *tmp_decl = - new vhdl_signal_decl(ss.str().c_str(), tmp_type); + vhdl_signal_decl *tmp_decl = new vhdl_signal_decl(ss.str(), tmp_type); arch->get_scope()->add_decl(tmp_decl); int nin = ivl_udp_nin(udp); diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc index 5c867ab8d..28c5b0c5c 100644 --- a/tgt-vhdl/scope.cc +++ b/tgt-vhdl/scope.cc @@ -1,7 +1,7 @@ /* * VHDL code generation for scopes. * - * Copyright (C) 2008-2013 Nick Gasson (nick@nickg.me.uk) + * Copyright (C) 2008-2014 Nick Gasson (nick@nickg.me.uk) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -204,7 +204,7 @@ void draw_nexus(ivl_nexus_t nexus) ostringstream ss; ss << "LO" << ivl_logic_basename(log); - vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type)); + vhdl_scope->add_decl(new vhdl_signal_decl(ss.str(), type)); link_scope_to_nexus_tmp(priv, vhdl_scope, ss.str()); } @@ -251,7 +251,7 @@ void draw_nexus(ivl_nexus_t nexus) ss << ivl_lpm_basename(lpm); if (!vhdl_scope->have_declared(ss.str())) - vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type)); + vhdl_scope->add_decl(new vhdl_signal_decl(ss.str(), type)); link_scope_to_nexus_tmp(priv, vhdl_scope, ss.str()); } @@ -561,7 +561,7 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, vhdl_type *array_type = vhdl_type::array_of(base_type, type_name, msb, lsb); - vhdl_decl *array_decl = new vhdl_type_decl(type_name.c_str(), array_type); + vhdl_decl *array_decl = new vhdl_type_decl(type_name, array_type); ent->get_arch()->get_scope()->add_decl(array_decl); sig_type = new vhdl_type(*array_type); @@ -578,7 +578,7 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, switch (mode) { case IVL_SIP_NONE: { - vhdl_decl *decl = new vhdl_signal_decl(name.c_str(), sig_type); + vhdl_decl *decl = new vhdl_signal_decl(name, sig_type); ostringstream ss; if (ivl_signal_local(sig)) { @@ -612,11 +612,11 @@ static void declare_one_signal(vhdl_entity *ent, ivl_signal_t sig, // which represents the register std::string newname(name); newname += "_Reg"; - rename_signal(sig, newname.c_str()); + rename_signal(sig, newname); vhdl_type *reg_type = new vhdl_type(*sig_type); ent->get_arch()->get_scope()->add_decl - (new vhdl_signal_decl(newname.c_str(), reg_type)); + (new vhdl_signal_decl(newname, reg_type)); // Create a concurrent assignment statement to // connect the register to the output @@ -892,7 +892,7 @@ static int draw_task(ivl_scope_t scope, ivl_scope_t parent) signame += taskname; } - vhdl_signal_decl *decl = new vhdl_signal_decl(signame.c_str(), sigtype); + vhdl_signal_decl *decl = new vhdl_signal_decl(signame, sigtype); ostringstream ss; ss << "Declared at " << ivl_signal_file(sig) << ":" diff --git a/vhdlpp/Makefile.in b/vhdlpp/Makefile.in index da356cc13..15c9523ab 100644 --- a/vhdlpp/Makefile.in +++ b/vhdlpp/Makefile.in @@ -86,7 +86,11 @@ distclean: clean rm -f stamp-vhdlpp_config-h vhdlpp_config.h cppcheck: $(O:.o=.cc) - cppcheck --enable=all -f $(INCLUDE_PATH) $^ + cppcheck --enable=all -f \ + -UYY_USER_INIT \ + -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \ + -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \ + $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in cd ..; ./config.status --file=vhdlpp/$@ diff --git a/vhdlpp/scope.cc b/vhdlpp/scope.cc index c6f783628..b3fc8a5cc 100644 --- a/vhdlpp/scope.cc +++ b/vhdlpp/scope.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 2011-2014 Stephen Williams (steve@icarus.com) * Copyright CERN 2013 / Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it @@ -34,10 +34,8 @@ using namespace std; * accumulate new scope values. */ ScopeBase::ScopeBase(const ActiveScope&ref) +: use_constants_(ref.use_constants_), cur_constants_(ref.cur_constants_) { - use_constants_ = ref.use_constants_; - cur_constants_ = ref.cur_constants_; - merge(ref.old_signals_.begin(), ref.old_signals_.end(), ref.new_signals_.begin(), ref.new_signals_.end(), insert_iterator >( diff --git a/vvp/Makefile.in b/vvp/Makefile.in index b9e260adb..d7e8ce35e 100644 --- a/vvp/Makefile.in +++ b/vvp/Makefile.in @@ -106,6 +106,9 @@ distclean: clean cppcheck: $(O:.o=.cc) libvpi.c draw_tt.c cppcheck --enable=all -f --suppressions-list=$(srcdir)/cppcheck.sup \ + -UMODULE_DIR1 -UMODULE_DIR2 -UYY_USER_INIT \ + -UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \ + -UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \ --relative-paths=$(srcdir) $(INCLUDE_PATH) $^ Makefile: $(srcdir)/Makefile.in diff --git a/vvp/delay.cc b/vvp/delay.cc index b83100914..5f7adca3d 100644 --- a/vvp/delay.cc +++ b/vvp/delay.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2005-2012 Stephen Williams + * Copyright (c) 2005-2014 Stephen Williams * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -622,7 +622,7 @@ void vvp_fun_modpath::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit, out_at[idx] -= now; } - for (cur ++ ; cur != candidate_list.end() ; ++ cur ) { + for (++ cur ; cur != candidate_list.end() ; ++ cur ) { src = *cur; for (unsigned idx = 0 ; idx < 12 ; idx += 1) { vvp_time64_t tmp = src->wake_time_ + src->delay_[idx]; diff --git a/vvp/event.cc b/vvp/event.cc index de32d910a..47b3d143a 100644 --- a/vvp/event.cc +++ b/vvp/event.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2012 Stephen Williams (steve@icarus.com) + * Copyright (c) 2004-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -98,9 +98,8 @@ void schedule_evctl(__vpiHandle*handle, double value, evctl_vector::evctl_vector(vvp_net_ptr_t ptr, const vvp_vector4_t&value, unsigned off, unsigned wid, unsigned long ecount) -:evctl(ecount), value_(value) +:evctl(ecount), ptr_(ptr), value_(value) { - ptr_ = ptr; off_ = off; wid_ = wid; } diff --git a/vvp/logic.cc b/vvp/logic.cc index a4d28e5e7..4b856f112 100644 --- a/vvp/logic.cc +++ b/vvp/logic.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2010 Stephen Williams (steve@icarus.com) + * Copyright (c) 2001-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -281,7 +281,7 @@ void vvp_fun_muxr::recv_real(vvp_net_ptr_t ptr, double bit, break; default: - fprintf(stderr, "Unsupported port type %d.\n", ptr.port()); + fprintf(stderr, "Unsupported port type %u.\n", ptr.port()); assert(0); } diff --git a/vvp/part.cc b/vvp/part.cc index e34b02c74..fb158723a 100644 --- a/vvp/part.cc +++ b/vvp/part.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2010 Stephen Williams (steve@icarus.com) + * Copyright (c) 2004-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -254,7 +254,7 @@ bool vvp_fun_part_var::recv_vec4_(vvp_net_ptr_t port, const vvp_vector4_t&bit, base = tmp; break; default: - fprintf(stderr, "Unsupported port type %d.\n", port.port()); + fprintf(stderr, "Unsupported port type %u.\n", port.port()); assert(0); break; } diff --git a/vvp/vpi_tasks.cc b/vvp/vpi_tasks.cc index 90310b38b..3f0c325d9 100644 --- a/vvp/vpi_tasks.cc +++ b/vvp/vpi_tasks.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 2001-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -379,7 +379,7 @@ static vpiHandle sysfunc_put_4net_value(vpiHandle ref, p_vpi_value vp, int) break; default: - fprintf(stderr, "XXXX format=%d, vwid=%u\n", (int)vp->format, + fprintf(stderr, "XXXX format=%d, vwid=%d\n", (int)vp->format, rfp->vwid); assert(0); } diff --git a/vvp/vvp_net.cc b/vvp/vvp_net.cc index 0c29fa4b6..15f6fa5b3 100644 --- a/vvp/vvp_net.cc +++ b/vvp/vvp_net.cc @@ -183,8 +183,8 @@ void vvp_net_t::operator delete(void*) } vvp_net_t::vvp_net_t() +: out_(vvp_net_ptr_t(0,0)) { - out_ = vvp_net_ptr_t(0,0); fun = 0; fil = 0; } diff --git a/vvp/vvp_net_sig.cc b/vvp/vvp_net_sig.cc index 33ac37d38..82c570df5 100644 --- a/vvp/vvp_net_sig.cc +++ b/vvp/vvp_net_sig.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004-2013 Stephen Williams (steve@icarus.com) + * Copyright (c) 2004-2014 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -210,7 +210,7 @@ void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit, break; default: - fprintf(stderr, "Unsupported port type %d.\n", ptr.port()); + fprintf(stderr, "Unsupported port type %u.\n", ptr.port()); assert(0); break; } @@ -266,7 +266,7 @@ void vvp_fun_signal4_sa::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit break; default: - fprintf(stderr, "Unsupported port type %d.\n", ptr.port()); + fprintf(stderr, "Unsupported port type %u.\n", ptr.port()); assert(0); break; } @@ -490,7 +490,7 @@ void vvp_fun_signal_real_sa::recv_real(vvp_net_ptr_t ptr, double bit, break; default: - fprintf(stderr, "Unsupported port type %d.\n", ptr.port()); + fprintf(stderr, "Unsupported port type %u.\n", ptr.port()); assert(0); break; }