From 046893d97f11caf067eec2f52c56d52a03342725 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 19 Jan 2022 10:08:33 +0100 Subject: [PATCH] Make output ports with data type variables In SystemVerilog output ports are a variable if either: * They are explicitly declared a variable (with the `var` keyword) * There is no explicit net type, but a explicit data type This is in detail described in section 23.2.2.3 ("Rules for determining port kind, data type, and direction") of the LRM (1800-2017). E.g. ``` output x // Net output [1:0] x // Net output signed x // Net output wire x // Net output wire logic x // Net output var x // Variable output logic x // Variable output var logic x // Variable output int x // Variable output real x // Variable output string x // Variable output some_typedef x // Variable ``` At the moment the code checks for certain data types and only makes the output port a variable for those. And it is even different data types depending on whether the port is declared ANSI or non-ANSI style. Change this so that if a data type is specified and it is not a implicit data type (i.e. only ranges or `signed`) then the output is of type variable. This ensures consistent and correct behavior. Signed-off-by: Lars-Peter Clausen --- parse.y | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/parse.y b/parse.y index 1aaf24f64..5c4744081 100644 --- a/parse.y +++ b/parse.y @@ -4568,13 +4568,7 @@ port_declaration // output ports are implicitly (on the inside) // variables because "reg" is not valid syntax // here. - } else if (dynamic_cast ($4)) { - use_type = NetNet::IMPLICIT_REG; - } else if (dynamic_cast ($4)) { - use_type = NetNet::IMPLICIT_REG; - } else if (dynamic_cast ($4)) { - use_type = NetNet::IMPLICIT_REG; - } else if (dynamic_cast ($4)) { + } else if ($4) { use_type = NetNet::IMPLICIT_REG; } } @@ -5026,13 +5020,8 @@ module_item // output ports are implicitly (on the inside) // variables because "reg" is not valid syntax // here. - } else if (dynamic_cast ($3)) { + } else if ($3) { use_type = NetNet::IMPLICIT_REG; - } else if (dynamic_cast ($3)) { - use_type = NetNet::IMPLICIT_REG; - } else if (enum_type_t*etype = dynamic_cast ($3)) { - if(etype->base_type == IVL_VT_LOGIC) - use_type = NetNet::IMPLICIT_REG; } if (use_type == NetNet::NONE) pform_set_port_type(@2, $4, NetNet::POUTPUT, $3, $1);