From 045a1b9808fa6c4782ddd42f7490c2869a1ed06d Mon Sep 17 00:00:00 2001 From: Prasad Joshi Date: Tue, 28 Jun 2011 14:59:02 +0100 Subject: [PATCH] Add support for variable of primitive data type 'logic' Verilog allows user to define variables of primitive types. The patch adds support for defining variables of type 'logic'. The data type 'logic' is the only primitive data type which supports defining ranges. Signed-off-by: Prasad Joshi --- parse.y | 7 +++++++ vvp/vpi_signal.cc | 1 + 2 files changed, 8 insertions(+) diff --git a/parse.y b/parse.y index 0d152149d..b1095a6fb 100644 --- a/parse.y +++ b/parse.y @@ -611,6 +611,13 @@ block_item_decl pform_set_net_range($5, $4, $3, IVL_VT_BOOL); if ($1) delete $1; } + + | attribute_list_opt K_logic unsigned_signed_opt range_opt + register_variable_list ';' + { + pform_set_net_range($5, $4, $3, IVL_VT_LOGIC); + if ($1) delete $1; + } /* Integer atom declarations are simpler in that they do not have all the trappings of a general variable declaration. All of that is implicit in the "integer" of the declaration. */ diff --git a/vvp/vpi_signal.cc b/vvp/vpi_signal.cc index 1c1542d01..f51ccee52 100644 --- a/vvp/vpi_signal.cc +++ b/vvp/vpi_signal.cc @@ -510,6 +510,7 @@ struct __vpiSignal* vpip_signal_from_handle(vpiHandle ref) switch (ref->vpi_type->type_code) { case vpiNet: case vpiReg: + /* This handles both reg and logic */ case vpiIntegerVar: case vpiByteVar: case vpiShortIntVar: