diff --git a/examples/hello.vl b/examples/hello.vl
index d04736522..2ac98814d 100644
--- a/examples/hello.vl
+++ b/examples/hello.vl
@@ -25,7 +25,7 @@
   *
   *  Compile this program with the command:
   *
-  *      verilog hello.vl
+  *      iverilog -ohello hello.vl
   *  
   *  After churning for a little while, the program will create the output
   *  file "hello" which is compiled, linked and ready to run. Run this
@@ -33,7 +33,9 @@
   *  
   *      ./hello
   *  
-  *  and the program will print the message to its output. Easy!
+  *  and the program will print the message to its output. Easy! For
+  *  more on how to make the iverilog command work, see the iverilog
+  *  manual page.
   */
 
 module main();
diff --git a/examples/show_vcd.vl b/examples/show_vcd.vl
index bbb5a322d..77f3edf23 100644
--- a/examples/show_vcd.vl
+++ b/examples/show_vcd.vl
@@ -24,7 +24,7 @@
   *  Like any other Verilog simulation, compile this program with the
   *  command:
   *  
-  *      verilog show_vcd.vl
+  *      iverilog show_vcd.vl
   *  
   *  This will generate the show_vcd command in the current directory.
   *  When you run the command, you will see the output from all the
diff --git a/examples/sqrt.vl b/examples/sqrt.vl
index 76741c66a..233eeeeb0 100644
--- a/examples/sqrt.vl
+++ b/examples/sqrt.vl
@@ -16,9 +16,22 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  *
- *   $Id: sqrt.vl,v 1.1 1999/12/05 21:08:56 steve Exp $"
+ *   $Id: sqrt.vl,v 1.2 2000/09/23 17:46:11 steve Exp $"
  */
 
+ /*
+  * This example shows that Icarus Verilog can run non-trivial
+  * programs, too. This uses a variety of Verilog language features
+  * to implement the module of a square-root device. The program
+  * uses IEEE1364-1995 language features and should work correctly
+  * on any Verilog compiler.
+  *
+  * Run the file with Icarus Verilog under UNIX using the command:
+  *
+  *     % iverilog -osqrt sqrt.v
+  *     % ./sqrt
+  */
+
  /*
   * This module approximates the square root of an unsigned 32bit
   * number. The algorithm works by doing a bit-wise binary search.
diff --git a/examples/xnf_add.vl b/examples/xnf_add.vl
index bd42dfa3c..7f7d65cc3 100644
--- a/examples/xnf_add.vl
+++ b/examples/xnf_add.vl
@@ -28,7 +28,8 @@
  *    iverilog -txnf -fpart=XC4010XLPQ160 -fncf=xnf_add.ncf -oxnf_add.xnf xnf_add.v
  *
  * That command causes an xnf_add.xnf and xnf_add.ncf file to be created.
- * Next, make the xnf_add.ngd file with the command:
+ * Next, Use Xilinx Alliance or Foundation tools to make the xnf_add.ngd
+ * file with the command:
  *
  *    xnf2ngd -l xilinxun -u xnf_add.xnf xnf_add.ngo
  *    ngdbuild xnf_add.ngo xnf_add.ngd
@@ -40,8 +41,8 @@
  *    map -o map.ncd xnf_add.ngd
  *    par -w map.ncd xnf_add.ncd
  *
- * At this point, you can use the FPGA Editor to edit the xnf_add.ncd
- * file to see the carry chains made up to support the adder.
+ * At this point, you can use the Xilinx FPGA Editor to edit the xnf_add.ncd
+ * file and see the carry chains made up to support the adder.
  */
 
 module main;