From 035325e9dfbb2f647fbccf9184ddeaca2e24bf79 Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Sun, 27 Feb 2022 14:21:22 -0800
Subject: [PATCH] Regression test for issue 576.

---
 ivtest/ivltests/issue576.v | 15 +++++++++++++++
 ivtest/regress-sv.list     |  1 +
 2 files changed, 16 insertions(+)
 create mode 100644 ivtest/ivltests/issue576.v

diff --git a/ivtest/ivltests/issue576.v b/ivtest/ivltests/issue576.v
new file mode 100644
index 000000000..fee1b92b7
--- /dev/null
+++ b/ivtest/ivltests/issue576.v
@@ -0,0 +1,15 @@
+
+// This example is rediculous, but legal. However, Icarus Verilog will print
+// various warnings about this. The warnings are OK, but Issue#576 saw this
+// program assert, which is worse.
+module test;
+   function void fun;
+      begin
+	 $display("PASSED");
+	 $finish;
+      end
+   endfunction // fun
+
+   always_comb fun;
+   
+endmodule
diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list
index d3c79049f..88f1abd99 100644
--- a/ivtest/regress-sv.list
+++ b/ivtest/regress-sv.list
@@ -622,3 +622,4 @@ br_gh436		normal,-g2012		ivltests gold=br_gh436.gold
 br_gh451		normal,-g2012,-Ptest.foo=4	ivltests gold=br_gh451.gold
 br_gh453		normal,-g2012		ivltests
 br_gh460		normal,-g2012		ivltests
+issue576		normal,-g2012		ivltests