From 026d552be143d583540b33b35ad991c12a299b84 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Mar 2022 11:01:09 +0100 Subject: [PATCH] Add regression test for module port range mismatch Check that a range mismatch is detected for non-ANSI module ports when port direction and data type are declared separately. An error should be reported and no crash should occur. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_port_range_mismatch.v | 16 ++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 17 insertions(+) create mode 100644 ivtest/ivltests/module_port_range_mismatch.v diff --git a/ivtest/ivltests/module_port_range_mismatch.v b/ivtest/ivltests/module_port_range_mismatch.v new file mode 100644 index 000000000..07cd1082d --- /dev/null +++ b/ivtest/ivltests/module_port_range_mismatch.v @@ -0,0 +1,16 @@ +// Check that range mismatches between port direction and data type are detected +// for module ports. An error should be reported and no crash should occur. + +module test; + input [1:0] x; + wire [3:0] x; + + wire [3:0] y; + + assign y = x; + + initial begin + $display("FAILED"); + end + +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 09d213229..5306833bc 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -648,6 +648,7 @@ module_inout_port_type CE ivltests module_input_port_type CE ivltests module_output_port_var1 normal ivltests module_output_port_var2 normal ivltests +module_port_range_mismatch CE ivltests modulus normal ivltests # wire % and reg % operators modulus2 normal ivltests # reg % operators monitor normal ivltests gold=monitor.gold