diff --git a/vvp/Makefile.in b/vvp/Makefile.in
index 856a4fd5f..df4404a57 100644
--- a/vvp/Makefile.in
+++ b/vvp/Makefile.in
@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.63 2004/12/29 23:45:13 steve Exp $"
+#ident "$Id: Makefile.in,v 1.64 2005/02/03 04:55:13 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -82,8 +82,8 @@ vpi_memory.o vpi_vthr_vector.o vpip_bin.o vpip_hex.o vpip_oct.o \
 vpip_to_dec.o vpip_format.o vvp_vpi.o
 
 O = main.o parse.o parse_misc.o lexor.o arith.o bufif.o compile.o concat.o \
-functor.o fvectors.o npmos.o part.o resolv.o stop.o symbols.o ufunc.o \
-codes.o \
+functor.o fvectors.o npmos.o part.o reduce.o resolv.o stop.o symbols.o \
+ufunc.o codes.o \
 vthread.o schedule.o statistics.o tables.o udp.o vvp_net.o memory.o \
 force.o event.o logic.o delay.o words.o $V
 
diff --git a/vvp/README.txt b/vvp/README.txt
index 2547bf345..706a5a17e 100644
--- a/vvp/README.txt
+++ b/vvp/README.txt
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
  *
- *  $Id: README.txt,v 1.55 2005/01/28 05:34:25 steve Exp $
+ *  $Id: README.txt,v 1.56 2005/02/03 04:55:13 steve Exp $
  */
 
 VVP SIMULATION ENGINE
@@ -482,6 +482,24 @@ The initial output value is (W+X+Y+Z) bits of 'bx. As input values are
 propagated, the bits are placed in the correct place in the output
 vector value, and a new output value is propagated.
 
+
+REDUCTION LOGIC
+
+The reduction logic statements take in a single vector, and propagate
+a single bit.
+
+        <label> .reduce/and  <symbol> ;
+        <label> .reduce/or   <symbol> ;
+        <label> .reduce/xor  <symbol> ;
+        <label> .reduce/nand <symbol> ;
+        <label> .reduce/nor  <symbol> ;
+        <label> .reduce/xnor <symbol> ;
+
+the device has a single input, which is a vector of any width. The
+device performs the logic on all the bits of the vector (a la Verilog)
+and produces and propagates a single bit width vector.
+
+
 FORCE STATEMENTS (old method - remove me):
 
 A force statement creates functors that represent a Verilog force
diff --git a/vvp/compile.h b/vvp/compile.h
index adad637d2..4f5089a44 100644
--- a/vvp/compile.h
+++ b/vvp/compile.h
@@ -1,7 +1,7 @@
 #ifndef __compile_H
 #define __compile_H
 /*
- * Copyright (c) 2001-2004 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2001-2005 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compile.h,v 1.60 2005/01/22 01:06:20 steve Exp $"
+#ident "$Id: compile.h,v 1.61 2005/02/03 04:55:13 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -134,6 +134,13 @@ extern void compile_cmp_ge(char*label, long width, bool signed_flag,
 			   unsigned argc, struct symb_s*argv);
 extern void compile_cmp_gt(char*label, long width, bool signed_flag,
 			   unsigned argc, struct symb_s*argv);
+extern void compile_reduce_and(char*label, struct symb_s arg);
+extern void compile_reduce_or(char*label, struct symb_s arg);
+extern void compile_reduce_xor(char*label, struct symb_s arg);
+extern void compile_reduce_nand(char*label, struct symb_s arg);
+extern void compile_reduce_nor(char*label, struct symb_s arg);
+extern void compile_reduce_xnor(char*label, struct symb_s arg);
+
 extern void compile_shiftl(char*label, long width,
 			   unsigned argc, struct symb_s*argv);
 extern void compile_shiftr(char*label, long width,
@@ -287,6 +294,9 @@ extern void compile_net(char*label, char*name,
 
 /*
  * $Log: compile.h,v $
+ * Revision 1.61  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
  * Revision 1.60  2005/01/22 01:06:20  steve
  *  Implement the .cmp/eeq LPM node.
  *
diff --git a/vvp/lexor.lex b/vvp/lexor.lex
index b90f9b025..90c116198 100644
--- a/vvp/lexor.lex
+++ b/vvp/lexor.lex
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: lexor.lex,v 1.47 2005/01/22 01:06:20 steve Exp $"
+#ident "$Id: lexor.lex,v 1.48 2005/02/03 04:55:13 steve Exp $"
 #endif
 
 # include  "parse_misc.h"
@@ -105,6 +105,12 @@
 ".param"    { return K_PARAM; }
 ".part"     { return K_PART; }
 ".part/pv"  { return K_PART_PV; }
+".reduce/and" { return K_REDUCE_AND; }
+".reduce/or"  { return K_REDUCE_OR; }
+".reduce/xor" { return K_REDUCE_XOR; }
+".reduce/nand" { return K_REDUCE_NAND; }
+".reduce/nor"  { return K_REDUCE_NOR; }
+".reduce/xnor" { return K_REDUCE_XNOR; }
 ".resolv"   { return K_RESOLV; }
 ".scope"    { return K_SCOPE; }
 ".shift/l"  { return K_SHIFTL; }
@@ -186,6 +192,9 @@ int yywrap()
 
 /*
  * $Log: lexor.lex,v $
+ * Revision 1.48  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
  * Revision 1.47  2005/01/22 01:06:20  steve
  *  Implement the .cmp/eeq LPM node.
  *
diff --git a/vvp/parse.y b/vvp/parse.y
index 8f6008afb..1a7f19a2e 100644
--- a/vvp/parse.y
+++ b/vvp/parse.y
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: parse.y,v 1.64 2005/01/22 01:06:20 steve Exp $"
+#ident "$Id: parse.y,v 1.65 2005/02/03 04:55:13 steve Exp $"
 #endif
 
 # include  "parse_misc.h"
@@ -62,6 +62,8 @@ extern FILE*yyin;
 %token K_CMP_EEQ K_CMP_EQ K_CMP_NE K_CMP_GE K_CMP_GE_S K_CMP_GT K_CMP_GT_S
 %token K_CONCAT
 %token K_EVENT K_EVENT_OR K_FUNCTOR K_NET K_NET_S K_PARAM K_PART K_PART_PV
+%token K_REDUCE_AND K_REDUCE_OR K_REDUCE_XOR
+%token K_REDUCE_NAND K_REDUCE_NOR K_REDUCE_XNOR
 %token K_RESOLV K_SCOPE K_SHIFTL K_SHIFTR K_THREAD K_TIMESCALE K_UFUNC
 %token K_UDP K_UDP_C K_UDP_S
 %token K_MEM K_MEM_P K_MEM_I
@@ -270,6 +272,23 @@ statement
 		  compile_cmp_gt($1, $3, true, obj.cnt, obj.vect);
 		}
 
+        | T_LABEL K_REDUCE_AND symbol ';'
+                { compile_reduce_and($1, $3); }
+
+        | T_LABEL K_REDUCE_OR symbol ';'
+                { compile_reduce_or($1, $3); }
+
+        | T_LABEL K_REDUCE_XOR symbol ';'
+                { compile_reduce_xor($1, $3); }
+
+        | T_LABEL K_REDUCE_NAND symbol ';'
+                { compile_reduce_nand($1, $3); }
+
+        | T_LABEL K_REDUCE_NOR symbol ';'
+                { compile_reduce_nor($1, $3); }
+
+        | T_LABEL K_REDUCE_XNOR symbol ';'
+                { compile_reduce_xnor($1, $3); }
 
 	| T_LABEL K_SHIFTL T_NUMBER ',' symbols ';'
 		{ struct symbv_s obj = $5;
@@ -650,6 +669,9 @@ int compile_design(const char*path)
 
 /*
  * $Log: parse.y,v $
+ * Revision 1.65  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
  * Revision 1.64  2005/01/22 01:06:20  steve
  *  Implement the .cmp/eeq LPM node.
  *
diff --git a/vvp/reduce.cc b/vvp/reduce.cc
new file mode 100644
index 000000000..008b697da
--- /dev/null
+++ b/vvp/reduce.cc
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2005 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: reduce.cc,v 1.1 2005/02/03 04:55:13 steve Exp $"
+#endif
+
+# include  "compile.h"
+# include  "schedule.h"
+# include  <limits.h>
+# include  <stdio.h>
+# include  <assert.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+
+class vvp_reduce_and  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_and();
+      ~vvp_reduce_and();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_and::vvp_reduce_and()
+{
+}
+
+vvp_reduce_and::~vvp_reduce_and()
+{
+}
+
+void vvp_reduce_and::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_1;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res & bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+class vvp_reduce_or  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_or();
+      ~vvp_reduce_or();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_or::vvp_reduce_or()
+{
+}
+
+vvp_reduce_or::~vvp_reduce_or()
+{
+}
+
+void vvp_reduce_or::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_0;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res | bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+class vvp_reduce_xor  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_xor();
+      ~vvp_reduce_xor();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_xor::vvp_reduce_xor()
+{
+}
+
+vvp_reduce_xor::~vvp_reduce_xor()
+{
+}
+
+void vvp_reduce_xor::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_0;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res ^ bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+class vvp_reduce_nand  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_nand();
+      ~vvp_reduce_nand();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_nand::vvp_reduce_nand()
+{
+}
+
+vvp_reduce_nand::~vvp_reduce_nand()
+{
+}
+
+void vvp_reduce_nand::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_1;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res & bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, ~res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+class vvp_reduce_nor  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_nor();
+      ~vvp_reduce_nor();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_nor::vvp_reduce_nor()
+{
+}
+
+vvp_reduce_nor::~vvp_reduce_nor()
+{
+}
+
+void vvp_reduce_nor::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_0;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res | bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, ~res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+class vvp_reduce_xnor  : public vvp_net_fun_t {
+
+    public:
+      vvp_reduce_xnor();
+      ~vvp_reduce_xnor();
+      void recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit);
+};
+
+vvp_reduce_xnor::vvp_reduce_xnor()
+{
+}
+
+vvp_reduce_xnor::~vvp_reduce_xnor()
+{
+}
+
+void vvp_reduce_xnor::recv_vec4(vvp_net_ptr_t prt, vvp_vector4_t bit)
+{
+      vvp_bit4_t res =  BIT4_0;
+
+      for (unsigned idx = 0 ;  idx < bit.size() ;  idx += 1)
+	    res = res ^ bit.value(idx);
+
+      vvp_vector4_t rv (1);
+      rv.set_bit(0, ~res);
+      vvp_send_vec4(prt.ptr()->out, rv);
+}
+
+static void make_reduce(char*label, vvp_net_fun_t*red, struct symb_s arg)
+{
+      vvp_net_t*ptr = new vvp_net_t;
+      ptr->fun = red;
+
+      define_functor_symbol(label, ptr);
+      free(label);
+
+      input_connect(ptr, 0, arg.text);
+}
+
+void compile_reduce_and(char*label, struct symb_s arg)
+{
+      vvp_reduce_and* reduce = new vvp_reduce_and;
+      make_reduce(label, reduce, arg);
+}
+
+void compile_reduce_or(char*label, struct symb_s arg)
+{
+      vvp_reduce_or* reduce = new vvp_reduce_or;
+      make_reduce(label, reduce, arg);
+}
+
+void compile_reduce_xor(char*label, struct symb_s arg)
+{
+      vvp_reduce_xor* reduce = new vvp_reduce_xor;
+      make_reduce(label, reduce, arg);
+}
+
+void compile_reduce_nand(char*label, struct symb_s arg)
+{
+      vvp_reduce_nand* reduce = new vvp_reduce_nand;
+      make_reduce(label, reduce, arg);
+}
+
+void compile_reduce_nor(char*label, struct symb_s arg)
+{
+      vvp_reduce_nor* reduce = new vvp_reduce_nor;
+      make_reduce(label, reduce, arg);
+}
+
+void compile_reduce_xnor(char*label, struct symb_s arg)
+{
+      vvp_reduce_xnor* reduce = new vvp_reduce_xnor;
+      make_reduce(label, reduce, arg);
+}
+
+/*
+ * $Log: reduce.cc,v $
+ * Revision 1.1  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
+ */
diff --git a/vvp/vvp_net.cc b/vvp/vvp_net.cc
index 51ae6e396..994e85efd 100644
--- a/vvp/vvp_net.cc
+++ b/vvp/vvp_net.cc
@@ -16,7 +16,7 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: vvp_net.cc,v 1.11 2005/01/30 05:06:49 steve Exp $"
+#ident "$Id: vvp_net.cc,v 1.12 2005/02/03 04:55:13 steve Exp $"
 
 # include  "vvp_net.h"
 # include  <stdio.h>
@@ -26,12 +26,14 @@
 /* *** BIT operations *** */
 vvp_bit4_t add_with_carry(vvp_bit4_t a, vvp_bit4_t b, vvp_bit4_t&c)
 {
-      if ((a|b|c) > 1) {
+      if (bit4_is_xz(a) || bit4_is_xz(b) || bit4_is_xz(c)) {
 	    c = BIT4_X;
 	    return BIT4_X;
       }
 
-      int sum = a + b + c;
+	// NOTE: This relies on the facts that XZ values have been
+	// weeded out, and that BIT4_1 is 1 and BIT4_0 is 0.
+      int sum = (int)a + (int)b + (int)c;
 
       switch (sum) {
 	  case 0:
@@ -72,6 +74,32 @@ vvp_bit4_t operator & (vvp_bit4_t a, vvp_bit4_t b)
       return BIT4_1;
 }
 
+vvp_bit4_t operator | (vvp_bit4_t a, vvp_bit4_t b)
+{
+      if (a == BIT4_1)
+	    return BIT4_1;
+      if (b == BIT4_1)
+	    return BIT4_1;
+      if (bit4_is_xz(a))
+	    return BIT4_X;
+      if (bit4_is_xz(b))
+	    return BIT4_X;
+      return BIT4_0;
+}
+
+vvp_bit4_t operator ^ (vvp_bit4_t a, vvp_bit4_t b)
+{
+      if (bit4_is_xz(a))
+	    return BIT4_X;
+      if (bit4_is_xz(b))
+	    return BIT4_X;
+      if (a == BIT4_0)
+	    return b;
+      if (b == BIT4_0)
+	    return a;
+      return BIT4_0;
+}
+
 vvp_bit4_t operator ~ (vvp_bit4_t a)
 {
       switch (a) {
@@ -864,6 +892,9 @@ vvp_bit4_t compare_gtge_signed(const vvp_vector4_t&a,
 
 /*
  * $Log: vvp_net.cc,v $
+ * Revision 1.12  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
  * Revision 1.11  2005/01/30 05:06:49  steve
  *  Get .arith/sub working.
  *
diff --git a/vvp/vvp_net.h b/vvp/vvp_net.h
index 130177c66..ca9c5b5b8 100644
--- a/vvp/vvp_net.h
+++ b/vvp/vvp_net.h
@@ -18,7 +18,7 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: vvp_net.h,v 1.11 2005/01/30 05:06:49 steve Exp $"
+#ident "$Id: vvp_net.h,v 1.12 2005/02/03 04:55:13 steve Exp $"
 
 # include  <assert.h>
 
@@ -56,6 +56,8 @@ extern bool bit4_is_xz(vvp_bit4_t a);
      for 4-value bit operations. */
 extern vvp_bit4_t operator ~ (vvp_bit4_t a);
 extern vvp_bit4_t operator & (vvp_bit4_t a, vvp_bit4_t b);
+extern vvp_bit4_t operator | (vvp_bit4_t a, vvp_bit4_t b);
+extern vvp_bit4_t operator ^ (vvp_bit4_t a, vvp_bit4_t b);
 
 /*
  * This class represents scaler values collected into vectors. The
@@ -509,6 +511,9 @@ class vvp_fun_signal  : public vvp_net_fun_t {
 
 /*
  * $Log: vvp_net.h,v $
+ * Revision 1.12  2005/02/03 04:55:13  steve
+ *  Add support for reduction logic gates.
+ *
  * Revision 1.11  2005/01/30 05:06:49  steve
  *  Get .arith/sub working.
  *