From 0136db7ee71a6b62aacc5411ff938f0c80f904b7 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sat, 7 Sep 2024 17:52:28 +0100
Subject: [PATCH] Fix the return type of the $bits system function (issue
 #1163)

Early editions of the SystemVerilog standard did not specify the return
type for $bits, so we made it 32 bit unsigned 2-state. Later editions
state the return type is integer (32 bit signed 4-state), so make it so.
---
 elab_expr.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/elab_expr.cc b/elab_expr.cc
index f7828c83c..43d08c8b1 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -1437,10 +1437,10 @@ unsigned PECallFunction::test_width_sfunc_(Design*des, NetScope*scope,
 		  expr->test_width(des, scope, arg_mode);
 	    }
 
-	    expr_type_   = IVL_VT_BOOL;
+	    expr_type_   = IVL_VT_LOGIC;
 	    expr_width_  = integer_width;
 	    min_width_   = integer_width;
-            signed_flag_ = false;
+            signed_flag_ = true;
 
 	    if (debug_elaborate)
 		  cerr << get_fileline() << ": " << __func__ << ": "