diff --git a/elab_net.cc b/elab_net.cc
index 42c3ebee5..8fdadcc79 100644
--- a/elab_net.cc
+++ b/elab_net.cc
@@ -52,8 +52,10 @@ NetNet* PEConcat::elaborate_lnet_common_(Design*des, NetScope*scope,
       unsigned errors = 0;
 
       if (repeat_) {
-	    cerr << get_fileline() << ": sorry: I do not know how to"
-		  " elaborate repeat concatenation nets." << endl;
+	    cerr << repeat_->get_fileline() << ": error: "
+	         << "repeat concatenations are not allowed in net l-values."
+	         << endl;
+	    des->errors += 1;
 	    return 0;
       }
 
diff --git a/ivtest/gold/br_gh1178a.gold b/ivtest/gold/br_gh1178a.gold
new file mode 100644
index 000000000..451558c80
--- /dev/null
+++ b/ivtest/gold/br_gh1178a.gold
@@ -0,0 +1,4 @@
+./ivltests/br_gh1178a.v:12: error: repeat concatenations are not allowed in net l-values.
+./ivltests/br_gh1178a.v:12: error: Inout port expression must support continuous assignment.
+./ivltests/br_gh1178a.v:12:      : Port 2 (w) of net_connect is connected to {'sd2{bus}}
+2 error(s) during elaboration.
diff --git a/ivtest/ivltests/br_gh1178a.v b/ivtest/ivltests/br_gh1178a.v
new file mode 100644
index 000000000..d4bae3931
--- /dev/null
+++ b/ivtest/ivltests/br_gh1178a.v
@@ -0,0 +1,21 @@
+module net_connect #(parameter WIDTH=1) (w, w);
+  inout wire[WIDTH-1:0] w;
+endmodule
+
+
+module ReplicateMod (
+  inout wire [3:0] bus,
+  inout wire [7:0] replicated
+  );
+  // It is illegal to connect a replication to an output or inout port.
+  net_connect #(.WIDTH(8)) net_connect (replicated, ({2{bus}}));
+endmodule
+
+
+module tb;
+  logic [3:0] bus;
+  wire [7:0] replicated;
+  wire [3:0] wire__bus = bus;
+  ReplicateMod dut(.bus(wire__bus), .replicated(replicated));
+  initial $display("FAILED: this should be a compilation error.");
+endmodule
diff --git a/ivtest/ivltests/br_gh1178b.v b/ivtest/ivltests/br_gh1178b.v
new file mode 100644
index 000000000..90bc80803
--- /dev/null
+++ b/ivtest/ivltests/br_gh1178b.v
@@ -0,0 +1,40 @@
+module net_connect #(parameter WIDTH=1) (w, w);
+  inout wire[WIDTH-1:0] w;
+endmodule
+
+
+module ReplicateMod (
+  inout wire [3:0] bus,
+  inout wire [7:0] replicated
+  );
+  net_connect #(.WIDTH(8)) net_connect (replicated, ({bus, bus}));
+endmodule
+
+
+module tb;
+  logic passed;
+  logic [3:0] bus;
+  wire  [7:0] replicated;
+  wire  [3:0] wire__bus = bus;
+
+  ReplicateMod dut(.bus(wire__bus), .replicated(replicated));
+
+  initial begin
+    passed = 1'b1;
+    bus = 4'h3;
+    #1
+    if(replicated !== 8'h33) begin
+      passed = 1'b0;
+      $display("FAILED: Expected 'h33, but found 'h%x with inputs 'h%x", replicated, bus);
+    end
+    #1
+    bus = 4'hc;
+    #1
+    if(replicated !== 8'hcc) begin
+      passed = 1'b0;
+      $display("FAILED: Expected 'hcc, but found 'h%x with inputs 'h%x", replicated, bus);
+    end
+    #1
+    if (passed) $display("PASSED");
+  end
+endmodule
diff --git a/ivtest/ivltests/br_gh1178c.v b/ivtest/ivltests/br_gh1178c.v
new file mode 100644
index 000000000..6ef4fd465
--- /dev/null
+++ b/ivtest/ivltests/br_gh1178c.v
@@ -0,0 +1,42 @@
+module net_connect #(parameter WIDTH=1) (wo, w);
+  output wire[WIDTH-1:0] wo;
+  input  wire[WIDTH-1:0] w;
+  assign wo = w;
+endmodule
+
+
+module ReplicateMod (
+  input  wire [3:0] bus,
+  output wire [7:0] replicated
+  );
+  net_connect #(.WIDTH(8)) net_connect (replicated, ({2{bus}}));
+endmodule
+
+
+module tb;
+  logic passed;
+  logic [3:0] bus;
+  wire  [7:0] replicated;
+  wire  [3:0] wire__bus = bus;
+
+  ReplicateMod dut(.bus(wire__bus), .replicated(replicated));
+
+  initial begin
+    passed = 1'b1;
+    bus = 4'h3;
+    #1
+    if(replicated !== 8'h33) begin
+      passed = 1'b0;
+      $display("FAILED: Expected 'h33, but found 'h%x with inputs 'h%x", replicated, bus);
+    end
+    #1
+    bus = 4'hc;
+    #1
+    if(replicated !== 8'hcc) begin
+      passed = 1'b0;
+      $display("FAILED: Expected 'hcc, but found 'h%x with inputs 'h%x", replicated, bus);
+    end
+    #1
+    if (passed) $display("PASSED");
+  end
+endmodule
diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list
index 19ece7d66..dc09f946c 100644
--- a/ivtest/regress-vlg.list
+++ b/ivtest/regress-vlg.list
@@ -353,6 +353,9 @@ br_gh788		normal,-gno-io-range-error,-Wno-anachronisms	ivltests gold=br_gh788.go
 br_gh793		normal			ivltests
 br_gh827		normal			ivltests gold=br_gh827.gold
 br_gh889		normal,-gspecify	ivltests gold=br_gh889.gold
+br_gh1178a		CE			ivltests gold=br_gh1178a.gold
+br_gh1178b		normal			ivltests
+br_gh1178c		normal			ivltests
 br_ml20150315		normal			ivltests gold=br_ml_20150315.gold
 br_ml20150321		CE			ivltests
 br_mw20171108		normal			ivltests