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173 lines
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<!DOCTYPE html>
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<html lang="en" data-content_root="../../../">
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<title>Loadable Targets — Icarus Verilog documentation</title>
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<link rel="next" title="VVP - Verilog Virtual Processor" href="../vvp/index.html" />
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</head><body>
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<div class="documentwrapper">
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<div class="body" role="main">
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<section id="loadable-targets">
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<h1>Loadable Targets<a class="headerlink" href="#loadable-targets" title="Link to this heading">¶</a></h1>
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<p>Icarus Verilog supports dynamically loading code generator modules to
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perform the back-end processing of the completed design. The user
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specifies on the command line the module to load. The compiler loads
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the module (once the design is compiled and elaborated) and calls it
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to finally handle the design.</p>
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<p>Loadable target modules implement a set of functions that the core
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compiler calls to pass the design to it, and the module in turn uses a
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collection of functions in the core (the API) to access details of the
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design.</p>
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<section id="loading-target-modules">
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<h2>Loading Target Modules<a class="headerlink" href="#loading-target-modules" title="Link to this heading">¶</a></h2>
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<p>The target module loader is invoked with the ivl flag “-tdll”. That
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is, the DLL loader is a linked in target type. The name of the target
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module to load is then specified with the DLL flag, i.e. “-fDLL=<path>”.</p>
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</section>
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<section id="compiling-target-modules">
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<h2>Compiling Target Modules<a class="headerlink" href="#compiling-target-modules" title="Link to this heading">¶</a></h2>
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<p><write me></p>
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</section>
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<section id="loadable-target-module-api">
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<h2>Loadable Target Module Api<a class="headerlink" href="#loadable-target-module-api" title="Link to this heading">¶</a></h2>
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<p>The target module API is defined in the ivl_target.h header file. This
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declares all the type and functions that a loadable module needs to
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access the design.</p>
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</section>
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<section id="about-specific-expression-types">
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<h2>About Specific Expression Types<a class="headerlink" href="#about-specific-expression-types" title="Link to this heading">¶</a></h2>
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<p>In this section find notes about the various kinds of expression
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nodes. The notes here are in addition to the more general
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documentation in the ivl_target.h header file.</p>
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<ul>
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<li><p>IVL_EX_CONCAT</p>
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<p>The concatenation operator forms an expression node that holds the
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repeat count and all the parameter expressions. The repeat count is
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an integer that is calculated by the core compiler so it fully
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evaluated, and <em>not</em> an expression.</p>
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<p>The parameter expressions are retrieved by the ivl_expr_parm method,
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with the index increasing as parameters go from left to right, from
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most significant to least significant. (Note that this is different
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from the order of bits within an expression node.)</p>
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</li>
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<li><p>IVL_EX_NUMBER</p>
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<p>This is a constant number. The width is fully known, and the bit
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values are all represented by the ASCII characters 0, 1, x or z. The
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ivl_expr_bits method returns a pointer to the least significant bit,
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and the remaining bits are ordered from least significant to most
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significant. For example, 5’b1zzx0 is the 5 character string “0xzz1”.</p>
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</li>
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</ul>
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</section>
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</section>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<h1 class="logo"><a href="../../../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../../../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../../../targets/index.html">The Icarus Verilog Targets</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="../../index.html">Icarus Verilog Developer Support</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="../../getting_started.html">Getting Started as a Contributor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../version_stamps.html">Files With Version Information</a></li>
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<li class="toctree-l2 current"><a class="reference internal" href="../index.html">Developer Guide</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../glossary.html">Glossary</a></li>
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<li><a href="../../../index.html">Documentation overview</a><ul>
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<li><a href="index.html">IVL - The Core Compiler</a><ul>
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<li>Previous: <a href="lpm.html" title="previous chapter">What Is LPM</a></li>
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<li>Next: <a href="../vvp/index.html" title="next chapter">VVP - Verilog Virtual Processor</a></li>
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©2024-2025, Stephen Williams.
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