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iverilog/vhdlpp/vtype_emit.cc

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Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vtype.h"
# include <iostream>
# include <typeinfo>
# include <cassert>
using namespace std;
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
int VType::decl_t::emit(ostream&out, perm_string name) const
{
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
return type->emit(out, name, reg_flag);
}
int VTypeArray::emit(ostream&out, perm_string name, bool reg_flag) const
{
int errors = 0;
const VTypePrimitive*base = dynamic_cast<const VTypePrimitive*> (etype_);
assert(base != 0);
assert(dimensions() == 1);
if (reg_flag)
out << "reg ";
else
out << "wire ";
base->emit_primitive_type(out);
if (signed_flag_)
out << "signed ";
out << "[" << dimension(0).msb() << ":" << dimension(0).lsb() << "] ";
out << "\\" << name << " ";
return errors;
}
int VTypeEnum::emit(ostream&out, perm_string name, bool reg_flag) const
{
int errors = 0;
assert(0);
return errors;
}
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
int VTypePrimitive::emit_primitive_type(ostream&out) const
{
int errors = 0;
switch (type_) {
case BOOLEAN:
case BIT:
out << "bool ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
break;
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
case STDLOGIC:
out << "logic ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
break;
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
case INTEGER:
out << "bool [31:0] ";
break;
default:
assert(0);
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
break;
}
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
return errors;
}
int VTypePrimitive::emit(ostream&out, perm_string name, bool reg_flag) const
{
int errors = 0;
if (reg_flag)
out << "reg ";
else
out << "wire ";
errors += emit_primitive_type(out);
out << "\\" << name << " ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
return errors;
}
int VTypeRange::emit(ostream&out, perm_string name, bool reg_flag) const
{
int errors = 0;
assert(0);
return errors;
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
}