27 lines
641 B
VHDL
27 lines
641 B
VHDL
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library ieee;
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library uselib;
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use ieee.std_logic_1164.all;
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use uselib.work7.all;
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entity bigcount is
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port (clk, reset: in std_logic;
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count: out std_logic_vector (24 downto 0)
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);
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end entity bigcount;
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architecture bigcount_rtl of bigcount is
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signal d, t, q, myreset: std_logic;
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begin
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d <= t xor q;
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myreset <= reset or t;
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f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
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tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
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counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
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end bigcount_rtl;
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