28 lines
554 B
Coq
28 lines
554 B
Coq
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module bar(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output reg out;
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always @(posedge clk)
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if (rst) out <= 1'd0;
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else out <= ~inp;
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endmodule
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module foo(clk, rst, inp, out_a, out_b);
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input wire clk;
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input wire rst;
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input wire inp;
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output wire out_a;
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output wire out_b;
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bar bar_instance_1 ( (* this_is_clock *) .clk(clk), .rst(rst), .inp(inp), .out(out_a) );
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bar bar_instance_2 ( clk, (* this_is_reset *) rst, inp, out_b );
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initial begin
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$display("PASSED");
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end
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endmodule
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