41 lines
1003 B
Coq
41 lines
1003 B
Coq
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/*
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* This is a post-wynthesis test for the blif01a.v test. Run this
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* simulation in these steps:
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*
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* $ iverilog -tblif -o foo.blif blif01a.v
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* $ abc
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* abc 01> read_blif foo.blif
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* abc 02> write_verilog foo.v
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* abc 03> quit
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* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
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* $ vvp foo.vvp
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*/
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module main;
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parameter WID = 4;
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reg [WID-1:0] A, B;
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wire [WID:0] Q;
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addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]),
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.\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]),
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.\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));
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int adx;
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int bdx;
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initial begin
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for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
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for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
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A <= adx[WID-1:0];
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B <= bdx[WID-1:0];
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#1 if (Q !== (adx+bdx)) begin
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$display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
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$finish;
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end
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end
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end
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$display("PASSED");
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end
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endmodule // main
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