:vpi_module "system";

; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
;
;    This source code is free software; you can redistribute it
;    and/or modify it in source code form under the terms of the GNU
;    General Public License as published by the Free Software
;    Foundation; either version 2 of the License, or (at your option)
;    any later version.
;
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License
;    along with this program; if not, write to the Free Software
;    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA


; This example is similar to the code that the following Verilog program
; would make:
;
;    module main;
;       initial $display("Hello, World.");
;    endmodule
;
; This tests that a simple %vpi_call works properly. This is very nearly
; the mode trivial VVP source file that can generate any output.

main	.scope module, "main";

code
	%vpi_call 0 0 "$display", "Hello, World.";
	%end;
	.thread	code;
:file_names 2;
    "N/A";
    "<interactive>";
