diff --git a/iCE40-PLL-documentation.md b/iCE40-PLL-documentation.md
index 6919f6d..9e6a23d 100644
--- a/iCE40-PLL-documentation.md
+++ b/iCE40-PLL-documentation.md
@@ -8,6 +8,8 @@ This diagram is a much more faithful representation on what's going on that what
 # Dynamic reconfiguration
 
 The iCE40 PLL has a dynamic reconfiguration port.
+It can be enabled by setting the `TEST_MODE` parameter on the PLL instance.
+Note that when doing so, the static configuration is ignored and you HAVE TO use the dynamic reconfig port to load a valid config for the PLL to do anything !
 
 It's using 3 signals + the reset signal on the PLL :
 
@@ -51,8 +53,8 @@ The configuration word is 26 bits, or 27 bits for the UP5k :
     * `1`: `PHASE_AND_DELAY`
     * `3`: `EXTERNAL`
 * `pllout1Sel` and `pllout2Sel` are the output muxes
-    * `0`: `SHIFTREG_0deg`
-    * `1`: `SHIFTREG_90deg`
-    * `2`: `GENCLK`
-    * `3`: `GENCLK_HALF`
+    * `0`: `GENCLK`
+    * `1`: `GENCLK_HALF`
+    * `2`: `SHIFTREG_0deg`
+    * `3`: `SHIFTREG_90deg`