diff --git a/iCE40-PLL-documentation.md b/iCE40-PLL-documentation.md
index b4bb15c..95f663e 100644
--- a/iCE40-PLL-documentation.md
+++ b/iCE40-PLL-documentation.md
@@ -2,4 +2,57 @@
 
 This diagram is a much more faithful representation on what's going on that what's in the lattice docs.
 
-![PLL diagram](https://people.osmocom.org/~tnt/stuff/ice40/ice40_pll.svg)
\ No newline at end of file
+![PLL diagram](https://people.osmocom.org/~tnt/stuff/ice40/ice40_pll.svg)
+
+
+# Dynamic reconfiguration
+
+The iCE40 PLL has a dynamic reconfiguration port.
+
+It's using 3 signals + the reset signal on the PLL :
+
+```verilog
+output wire SDO,
+input  wire SDI,
+input  wire SCLK,
+input  wire RESETB,
+```
+
+And this is basically a shift register that allows you to change the internal configuration of the PLL by shifting it a new one.
+This must be done while the PLL is in reset (and so you can't depends on its output to be running to shift in the new config !), and the new configuration will become active once reset is released.
+
+Sequence would be : 
+* Assert the reset of your logic clocked by any PLL output
+* Assert `RESETB` (set to 0)
+* Shift in new config word 1 bit at a time, MSB first. Data is shifted in on the rising edge of `SCLK`
+* Release `RESETB`
+* Wait for `PLL_LOCK`
+* Release the reset of your logic clocked by PLL output
+
+The configuration word is 25 bits, or 26 bits for the UP5k :
+
+```
+[   26] ShiftReg[1]  (UP5k only)
+[   25] FSEnet
+[24:23] pllout1Sel
+[   22] Source Clock (0=Pad, 1=Fabric)
+[   21] ShiftReg[0]
+[20:19] pllout2Sel
+[18:17] delaymuxsel
+[16:14] FILTER_RANGE
+[13:11] DIVQ
+[10: 4] DIVF
+[ 3: 0] DIVR
+```
+
+* `FSEnet` is the mux right before `DIVF` in the diagram above. Set to `1` for `SIMPLE`
+* `delaymuxsel` is the feedback mux
+    * `0`: `DELAY`
+    * `1`: `PHASE_AND_DELAY`
+    * `3`: `EXTERNAL`
+* `pllout1Sel` and `pllout2Sel` are the output muxes
+    * `0`: `SHIFTREG_0deg`
+    * `1`: `SHIFTREG_90deg`
+    * `2`: `GENCLK`
+    * `3`: `GENCLK_HALF`
+