We have enough bits mapped that we can create a functional verilog model for almost all -bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144, as long as no -block memories or PLLs are used. (Both are fully documented, but the -icebox_vlog.py script does not create verilog models for them yet.) -
- --Next on the TODO list: PLLs, Timing Analysis, support for HX8K chips. +bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256.
-Here is the current snapshot of our toolchain: icestorm-snapshot-150526.zip
-This is work under construction and highly experimental! Use at your own risk!
+Installing the IceStorm Tools (icepack, icebox, iceprog):
-All snapshots in reverse chronological order: +
git clone https://github.com/cliffordwolf/icestorm.git icestorm +cd icestorm +make -j$(nproc) +sudo make install+ +
+Installing Arachne-PNR (the place&route tool):
-git clone https://github.com/cseed/arachne-pnr.git arachne-pnr +cd arachne-pnr +make -j$(nproc) +sudo make install+ +
+Installing Yosys (Verilog synthesis): +
+ +git clone https://github.com/cliffordwolf/yosys.git yosys +cd yosys +make -j$(nproc) +sudo make install+ +
-The tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser. +The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. +This files contain all the relevant information for arachne-pnr to place&route a design and +create an IceBox ASCII file for the placed and routed design. +
+ ++The IceStorm tools are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser.