2016-12-29 13:46:20 +01:00
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module top (
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input clk,
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output LED0,
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output LED1,
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output LED2,
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output LED3,
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output LED4,
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output LED5,
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output LED6,
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output LED7
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);
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localparam BITS = 3;
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localparam LOG2DELAY = 20;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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2017-01-09 21:21:15 +01:00
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always @(posedge clk) begin
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2016-12-29 13:46:20 +01:00
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counter <= counter + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} = 1 << outcnt;
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endmodule
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