diff --git a/src/map/scl/sclBufSize.c b/src/map/scl/sclBufSize.c
index 458196260..96b00af1c 100644
--- a/src/map/scl/sclBufSize.c
+++ b/src/map/scl/sclBufSize.c
@@ -88,6 +88,7 @@ Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, SC_BusPars * pPars )
         if ( pNtk->pWLoadUsed == NULL )
         {            
             p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(pNtk) );
+            if ( p->pWLoadUsed )
             pNtk->pWLoadUsed = Abc_UtilStrsav( p->pWLoadUsed->pName );
         }
         else
diff --git a/src/map/scl/sclLibUtil.c b/src/map/scl/sclLibUtil.c
index fb7cbd3a8..c078e4e32 100644
--- a/src/map/scl/sclLibUtil.c
+++ b/src/map/scl/sclLibUtil.c
@@ -272,7 +272,7 @@ SC_WireLoad * Abc_SclFindWireLoadModel( SC_Lib * p, float Area )
         pWLoadUsed = p->default_wire_load;
     else
     {
-        Abc_Print( 0, "No wire model given.\n" );
+//        Abc_Print( 0, "No wire model given.\n" );
         return NULL;
     }
     return Abc_SclFetchWireLoadModel( p, pWLoadUsed );
diff --git a/src/map/scl/sclSize.c b/src/map/scl/sclSize.c
index d5710af80..e06adc224 100644
--- a/src/map/scl/sclSize.c
+++ b/src/map/scl/sclSize.c
@@ -615,6 +615,7 @@ SC_Man * Abc_SclManStart( SC_Lib * pLib, Abc_Ntk_t * pNtk, int fUseWireLoads, in
         if ( pNtk->pWLoadUsed == NULL )
         {            
             p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(p->pNtk) );
+            if ( p->pWLoadUsed )
             pNtk->pWLoadUsed = Abc_UtilStrsav( p->pWLoadUsed->pName );
         }
         else