From 9545b79e0eafd2784b1170d20b80fd6b39262bb6 Mon Sep 17 00:00:00 2001
From: tklam <argama@gmail.com>
Date: Mon, 12 May 2025 10:20:13 -0400
Subject: [PATCH] support primitive gates with names in Verilog netlist

---
 src/base/ver/verCore.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c
index 183b1dedf..c74666804 100644
--- a/src/base/ver/verCore.c
+++ b/src/base/ver/verCore.c
@@ -1339,12 +1339,26 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga
         return 0;
     Ver_StreamMove( p );
 
-    // this is gate name - throw it away
+    // assume there is a gate name if the current char is not '(', e.g. xor g1 (z, a, b);
     if ( Ver_StreamPopChar(p) != '(' )
     {
-        sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." );
-        Ver_ParsePrintErrorMessage( pMan );
-        return 0;
+            // this is gate name - throw it away
+        pWord = Ver_ParseGetName( pMan );
+        if (pWord == NULL)
+        {
+            sprintf( pMan->sError, "Cannot parse a standard gate (expected a name before an opening parenthesis)." );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        else
+        {
+            if ( Ver_StreamPopChar(p) != '(' )
+            {
+                sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." );
+                Ver_ParsePrintErrorMessage( pMan );
+                return 0;
+            }
+        }
     }
     Ver_ParseSkipComments( pMan );