From 20f9095cf2e0440d041d4af106368c8db68a00c3 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Mon, 11 Sep 2023 12:14:57 +0700 Subject: [PATCH] Adding link to the fork of ABC with Agdmap. --- README.md | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 358f5ce9a..2bb34cd03 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,19 @@ # ABC: System for Sequential Logic Synthesis and Formal Verification -ABC is always changing but the current snapshot is believed to be stable. +ABC is always changing but the current snapshot is believed to be stable. + +## ABC fork with new features + +Here is a [fork](https://github.com/yongshiwo/abc.git) of ABC containing Agdmap, a novel technology mapper for LUT-based FPGAs. Agdmap is based on a technology mapping algorithm with adaptive gate decomposition [1]. It is a cut enumeration based mapping algorithm with bin packing for simultaneous wide gate decomposition, which is a patent pending technology. + +The mapper is developed and maintained by Longfei Fan and Prof. Chang Wu at Fudan University in Shanghai, China. The experimental results presented in [1] indicate that Agdmap can substantially improve area (by 10% or more) when compared against the best LUT mapping solutions in ABC, such as command "if". + +The source code is provided for research and evaluation only. For commercial usage, please contact Prof. Chang Wu at wuchang@fudan.edu.cn. + +References: + +[1] L. Fan and C. Wu, "FPGA technology mapping with adaptive gate decompostion", ACM/SIGDA FPGA International Symposium on FPGAs, 2023. ## Compiling: