From 00910e36ff1c104a24a3c2420cb53f49b02affc5 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Sat, 9 Aug 2025 17:00:02 -0700 Subject: [PATCH] Fixing typos. --- src/base/abci/abc.c | 8 ++++---- src/misc/util/utilPrefix.cpp | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c index 522def0b8..6b2e1493d 100644 --- a/src/base/abci/abc.c +++ b/src/base/abci/abc.c @@ -56846,9 +56846,9 @@ usage: Abc_Print( -2, "\t generates a prefix adder with minimum depth\n" ); Abc_Print( -2, "\t-N num : the bit-width of the adder [default = %d]\n", nBits ); Abc_Print( -2, "\t-F num : the limit on the fanout count [default = %d]\n", nFans ); - Abc_Print( -2, "\t-S num : the user's seed used to randomize search [default = %d]\n", Seed ); - Abc_Print( -2, "\t-I num : the number of iterations to find the smallest prefix [default = %d]\n", nIters ); - Abc_Print( -2, "\t-R num : the delay relaxation (the allowed level increase over log2(N)) [default = %d]\n", DelayRelax ); + Abc_Print( -2, "\t-S num : the random seed used to randomize search [default = %d]\n", Seed ); + Abc_Print( -2, "\t-I num : the number of iterations to find the smallest prefix tree [default = %d]\n", nIters ); + Abc_Print( -2, "\t-R num : the delay relaxation (the max allowed level increase over log2(N)) [default = %d]\n", DelayRelax ); Abc_Print( -2, "\t-d : toggles dumping the adder in Verilog [default = %s]\n", fDumpVer ? "yes": "no" ); Abc_Print( -2, "\t-m : toggles dumping the miter in Verilog [default = %s]\n", fDumpMiter ? "yes": "no" ); Abc_Print( -2, "\t-o : toggles using additional optimization [default = %s]\n", use_or ? "yes": "no" ); @@ -56856,7 +56856,7 @@ usage: Abc_Print( -2, "\t The code of this command is contributed by Martin PoviĊĦer \n\n" ); Abc_Print( -2, "\t The implementation is inspired by S. Roy, M. Choudhury, R. Puri, D. Pan,\n" ); Abc_Print( -2, "\t \"Polynomial time algorithm for area and power efficient adder synthesis\n" ); - Abc_Print( -2, "\t in high-performance designs\", Proc. ASP-DAC 2025.\n" ); + Abc_Print( -2, "\t in high-performance designs\", Proc. ASP-DAC 2015.\n" ); Abc_Print( -2, "\t https://www.cerc.utexas.edu/utda/publications/C166.pdf\n" ); return 1; } diff --git a/src/misc/util/utilPrefix.cpp b/src/misc/util/utilPrefix.cpp index bc99bc1d6..50db0723c 100644 --- a/src/misc/util/utilPrefix.cpp +++ b/src/misc/util/utilPrefix.cpp @@ -21,7 +21,7 @@ /* The implementation is inspired by S. Roy, M. Choudhury, R. Puri, D. Pan, "Polynomial time algorithm for area and power efficient adder synthesis - in high-performance designs", Proc. ASP-DAC 2025. + in high-performance designs", Proc. ASP-DAC 2015. https://www.cerc.utexas.edu/utda/publications/C166.pdf */