diff --git a/User-Documentation.md b/User-Documentation.md
index 19e50d3..eea729a 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -78,7 +78,7 @@ Finally are the **debug ports**, these are connected to relevant registers conta
 * Another example of constraint file is for the [Arty-S7 project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ARTY_S7/Arty-S7-50-Master.xdc#L87-L349), highlighted are the DDR3 pins. The Arty-S7 has x16 DDR3 and it works like two x8 (thus 2 `ddr3_dm`, 2 `ddr3_dqs`, and 16 `io_ddr3_dq`) <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>. 
 
 ### Note:  
-[1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.   
+[1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2 (not `DQ_BITS` of 16 or else the controller will not calibrate each bytes separately).  
 [2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.  
 [3]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).   
 [4]: This is the open-sourced [10Gb Ethernet Project](https://github.com/ZipCPU/eth10g).