From f6a153c817748767a6ffe9f72d81c0064b1c86dc Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 16 Nov 2023 12:05:14 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/User-Documentation.md b/User-Documentation.md index fc42c3a..ab5d63b 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -22,7 +22,6 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to | OPT_LOWPOWER | _has no effect yet_ | | OPT_BUS_ABORT | _has no effect yet_ | | MICRON_SIM | set to 1 if used in Micron DDR3 model to shorten power-on sequence, otherwise 0. | -| TEST_DATAMASK | set to 1 if datamask needs to be tested on the calibration sequence, otherwise 0. | | ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0. [[3]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) | | SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.| @@ -66,9 +65,13 @@ Below are the **auxiliary ports** associated with the main wishbone. This is not *** -After main wishbone port is the **second-wishbone ports**. This interface is only for debugging-purposes and would normally not be needed thus can be left unconnected. The ports for the second-wishbone is very much the same as the main wishbone. +After main wishbone port are the **second-wishbone ports**. This interface is only for debugging-purposes and would normally not be needed thus can be left unconnected by setting `SECOND_WISHBONE` = 0. The ports for the second-wishbone is very much the same as the main wishbone. -Finally is the **DDR3 I/O ports** +Next are the **DDR3 I/O ports**, these will be connected directly to the top-level pins of your design thus port-names must match what is indicated on your constraint file. You do not need to understand what each DDR3 I/O ports does but if you're curious, details on each DDR3 I/O pins are described on _2.10 Pinout Description_ from [JEDEC DDR3 doc (page 13)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf). + +Finally are the debug ports, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored. + +## Connecting to Top-Level DDR3 I/O Pins ### Note: