diff --git a/User-Documentation.md b/User-Documentation.md
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+++ b/User-Documentation.md
@@ -5,6 +5,8 @@ This memory controller is optimized to maintain a high data throughput and conti
 
 This design is [formally verified](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#lint-and-formal-verification) and [simulated using the Micron DDR3 model](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#simulation).
 
+
+
 # Getting Started
 The recommended way to instantiate this IP is to use the top module [`rtl/ddr3_top.v`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_top.v), a template for instantiation is also included in that file. Steps to include this DDR3 memory controller IP is to instantiate design, create the constraint file, then edit the localparams. 
 
@@ -181,4 +183,7 @@ This will run the DDR3 controller at 333 MHz (3 ns clock period) which is the [m
 - The [10Gb Ethernet Switch](https://github.com/ZipCPU/eth10g) project utilizes this DDR3 controller for accessing a single-rank DDR3 module (8 lanes of x8 DDR3) at DDR3-800 (100 MHz controller and 400 MHz PHY).
 
 # Other Open-Sourced DDR3 Controllers
-(soon...)
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+(soon...)
+
+# Developer Documentation 
+There is no developer documentation yet. But may I include here the [notes I compiled](https://github.com/AngeloJacobo/DDR3-Notes) when I did an intensive study on DDR3 before I started this project.
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