From dd35bf729090512d156981b8b5429a195b4988bb Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sun, 26 Nov 2023 11:26:31 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/User-Documentation.md b/User-Documentation.md index e1a19c2..294588f 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -147,7 +147,22 @@ Time Done: 497660 ns Average Rate: 47 ns/request -Notice how the average rate increased to 47 ns/request. Random access requires occasional precharge and activate which takes time and thus prolong the time for every read or write access. +Notice how the average rate increased to 47 ns/request. Random access requires occasional precharge and activate which takes time and thus prolong the time for every read or write access. At the very end of the report shows a summary: + +> TEST CALIBRATION +[-]: write_test_address_counter = 5000 +[-]: read_test_address_counter = 2000 +[-]: correct_read_data = 3499 +[-]: wrong_read_data = 0 + +> ------- SUMMARY ------- +Number of Writes = 4608 +Number of Reads = 4608 +Number of Success = 4604 +Number of Fails = 4 +Number of Injected Errors = 4 + +The summary under `TEST CALIBRATION` are the results from the **internal** read/write test as part of the internal calibration. These are the same counters on the waveform shown before where the `wrong_read_data` should be zero. Under `SUMMARY` is the report from the **external** read/write test where the top-level simulation file `ddr3_dimm_micron_sim.sv` sends read/write request to the DDR3 controller via the wishbone bus. Notice that the number of fails (4) matches the number of injected errors (4) which is only proper. # Sample Projects -