diff --git a/User-Documentation.md b/User-Documentation.md
index ea3f586..aa5c213 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -126,7 +126,12 @@ A part of internal test is to do alternate write then read consecutively as show
 There are counters for the number of correct and wrong read data during the internal read/write test: `correct_read_data` and `wrong_read_data`. As shown below, the `wrong_read_data` must remain zero while `correct_read_data` must increment until it reaches the maximum (3499 on this example).  
 ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/06d7b4c0-cd40-4fd1-9bc3-6329237e46e3)
 
+The simulation also reports the status of the simulation. For example, the report below:
+> [10000 ps]  RD @ (0,   840) -> [10000 ps]  RD @ (0,   848) -> [10000 ps]  RD @ (0,   856) -> [10000 ps]  RD @ (0,   864) -> [10000 ps]  RD @ (0,   872) -> 
 
+The format is [`time_delay`] `command` @ (`bank`, `address`).
+
+> [17500 ps] ACT @ (4, 10111) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10381) -> [17500 ps]  WR @ (0,   904) -> [10000 ps]  WR @ (4,   904)
 # Sample Projects
 -