From baf2592dc15e069f30483e22f0706903cdfbf6fa Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sun, 26 Nov 2023 12:03:47 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/User-Documentation.md b/User-Documentation.md index 15ce1db..c9f9381 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -112,9 +112,10 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e # Simulation -For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=%7B%22term%22%3A%22DDR3%20model%22%7D) is used. +For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=%7B%22term%22%3A%22DDR3%20model%22%7D) is used. Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado. `ddr3_dimm_micron_sim.sv` is the top-level module which instantiates both the DDR3 memory controller and the Micron DDR3 model. This module issues read and write requests to the controller via the wishbone bus, then the returned data from read requests are verified if it matches the data written. Both sequential and random accessesare tested. -Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks: + +After configuring, run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks: ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)