diff --git a/User-Documentation.md b/User-Documentation.md
index c6ea236..f64cc2b 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -44,7 +44,16 @@ Below are the main wishbone ports:
 | i_wb_stb   |  Strobe or transfer request signal. It's asserted (set to 1) to request a data transfer. | 
 | i_wb_we   | Write-enable signal. A high value (1) indicates a write operation, and a low value (0) indicates a read operation. | 
 | i_wb_addr  | Address bus. Used to specify the address for the current read or write operation. Formatted as {row, bank, column}. | 
-| i_wb_data   | Data bus for write operations. In a 4:1 controller, the data width is 8 times the data width `DQ_BITS`x`LANES`. | 
+| i_wb_data   | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `DQ_BITS`x`LANES`. | 
+| i_wb_sel   | Byte select for write operations. Indicates which bytes of the data bus are to be overwritten for the write operation. | 
+| o_wb_stall   | Indicates if the controller is busy (1)and cannot accept any new requests. | 
+| o_wb_ack   |  Acknowledgement signal. Indicates that a read or write request has been completed. | 
+| o_wb_data   | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `DQ_BITS`x`LANES`. 
+
+Extra ports associated to the main wishbone ports:
+| i_wb_data   | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `DQ_BITS`x`LANES`. | 
+
+
 
 **Note:**  
 [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.