From afc58c9515f6e28239605cfd2a2e74f2c9a9ab2a Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sat, 18 Nov 2023 10:43:47 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/User-Documentation.md b/User-Documentation.md index 38b2d71..7cd1c26 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -5,7 +5,10 @@ The goal of this documentation is to enable smooth transition when using this DD # Getting Started -The recommended way to instantiate this IP is to use the top module `rtl/ddr3_top.v`, a template for instantiation is also included in that file. The first thing to edit are the **top-level parameters**: +The recommended way to instantiate this IP is to use the top module `rtl/ddr3_top.v`, a template for instantiation is also included in that file. + +## Design Instantiation +The first thing to edit are the **top-level parameters**: | Parameter | Function | | :---: | :--- | @@ -77,6 +80,8 @@ Finally are the **debug ports**, these are connected to relevant registers conta * Another example of constraint file is for the [Arty-S7 project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ARTY_S7/Arty-S7-50-Master.xdc#L87-L349), highlighted are the DDR3 pins. The Arty-S7 has x16 DDR3 and it works like two x8 (thus 2 `ddr3_dm`, 2 `ddr3_dqs`, and 16 `io_ddr3_dq`) [[1]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) . Arty-S7 only has HR bank where the DDR3 is connected, this restricts the design to use on-chip split-termination [(UG471 7-Series Select Guide page 33)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO) for impedance matching instead of DCI used in HP banks. `IN_TERM UNTUNED_SPLIT_50` signifies that the input termination is set to an untuned split termination of 50 ohms. The constraint file was easily created by retrieving the pin constraints generated by the Vivado Memory Interface Generator (MIG) together with the [`.prj` file](https://github.com/Digilent/vivado-boards/blob/master/new/board_files/arty-s7-50/B.0/mig.prj#L47-L96) provided by Digilent for Arty-S7. The generated `.xdc` file by the MIG can be located at `[vivado_proj].gen/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc` +## Edit Localparams + ### Note: [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2 (not `DQ_BITS` of 16 or else the controller will not calibrate each bytes separately). [2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.