From 964770d62b020aae44f8185ecae31c198dd78dca Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Wed, 29 Nov 2023 18:52:20 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/User-Documentation.md b/User-Documentation.md index eb5aa49..2c4f246 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -1,7 +1,7 @@ # Specifications and Brief Description This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR. -Controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status and timing delay tracking, command issuing, and the PHY's internal calibration. The internal calibration handles the bitslip training, MPR (read calibration), write leveling (write calibration), +Controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration), The calibration is per-byte