From 89971158a2b9c3dbe94192b30c9c5a9ed5808657 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 16 Nov 2023 13:46:45 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/User-Documentation.md b/User-Documentation.md index e77af2f..639cb8c 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -73,9 +73,11 @@ Next are the **DDR3 I/O ports**, these will be connected directly to the top-lev Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored. ## Constraint File -Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389) [[4]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) , highlighted are all the DDR3 pins. This constraint file assumes a dual-rank DDR3 RAM (thus 2 pairs of `o_ddr3_clk`, `o_ddr3_cke`, `o_ddr3_s_n`, and `o_ddr3_odt`) with 8 lanes of x8 DDR3 (thus 8 `o_ddr3_dm`, 8 `io_ddr3_dqs`, and 64 `io_ddr3_dq`). +Example of constraint file is from the [Kintex-7 Ethernet Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389) [[4]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) , highlighted are all the DDR3 pins. This constraint file assumes a dual-rank DDR3 RAM (thus 2 pairs of `o_ddr3_clk`, `o_ddr3_cke`, `o_ddr3_s_n`, and `o_ddr3_odt`) with 8 lanes of x8 DDR3 (thus 8 `o_ddr3_dm`, 8 `io_ddr3_dqs`, and 64 `io_ddr3_dq`). -[The constraint file also has `set_property`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L453-L457) required for proper operation. The property `INTERNAL_VREF` must be set at half of the bank voltage (1.5V thus use `0.75`), and the property `BITSTREAM.STARTUP.MATCH_CYCLE` +[The constraint file also has `set_property`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L453-L457) required for proper operation. The property `INTERNAL_VREF` must be set to half of the bank voltage (1.5V thus use `0.75`). The property `BITSTREAM.STARTUP.MATCH_CYCLE` ([page 240 of UG628: Command Line Guide](https://docs.xilinx.com/v/u/en-US/devref)) is verified to work properly when value is `6`. + +Another example of constraint file is for the [Arty-S7 project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ARTY_S7/Arty-S7-50-Master.xdc#L87-L349). ### Note: [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.