From 856f33759964189f711777d9e2dff6b5ba8465b3 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 16 Nov 2023 13:32:46 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/User-Documentation.md b/User-Documentation.md index 061c125..e77af2f 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -75,6 +75,8 @@ Finally are the **debug ports**, these are connected to relevant registers conta ## Constraint File Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389) [[4]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) , highlighted are all the DDR3 pins. This constraint file assumes a dual-rank DDR3 RAM (thus 2 pairs of `o_ddr3_clk`, `o_ddr3_cke`, `o_ddr3_s_n`, and `o_ddr3_odt`) with 8 lanes of x8 DDR3 (thus 8 `o_ddr3_dm`, 8 `io_ddr3_dqs`, and 64 `io_ddr3_dq`). +[The constraint file also has `set_property`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L453-L457) required for proper operation. The property `INTERNAL_VREF` must be set at half of the bank voltage (1.5V thus use `0.75`), and the property `BITSTREAM.STARTUP.MATCH_CYCLE` + ### Note: [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2. [2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.