diff --git a/User-Documentation.md b/User-Documentation.md
index 1c864fe..259b9b6 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -111,12 +111,18 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e
 
 
 # Simulation
-Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation.     
+Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks:    
+
 
 ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)  
 
+`command_used` shows the command issued at a specific time. As shown below, during reads the `dqs` should toggle and `dq` should have a valid value, else they must be in high-impedance `Z`.  
+
 ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/a289066f-2a5c-4d08-9660-a76cf537383a)
 
+
+
+
 ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/817124fa-43d0-4e9f-94c4-2889614d7c87)
 
 ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/06d7b4c0-cd40-4fd1-9bc3-6329237e46e3)