From 454f87a5f9354b7c7ab7ef1556f85014bff4d923 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Wed, 29 Nov 2023 19:15:01 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/User-Documentation.md b/User-Documentation.md index 362e579..e7980f7 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -1,7 +1,7 @@ # Specifications and Brief Description -This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR. +This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) for an 8-lane x8 DDR3 module running at 800 MHz DDR, but this is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The user-interface is the basic Wishbone. -Controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration), and also an optional comprehensive read/write test. The internal read/write test include a burst access, random access, and alternating read-write access. Only if no error is found on this comprehensive read/write test will the calibration ends and user can start accessing the wishbone interface. +This memory controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's internal calibration. The PHY's internal calibration handles the bitslip training, read dqs alignment via MPR (read calibration), write dqs alignment via write leveling (write calibration), and also an optional comprehensive read/write test. The internal read/write test include a burst access, random access, and alternating read-write access tests. Only if no error is found on these tests will the calibration end and user can start accessing the wishbone interface. This design is formally verified and simulated using the Micron DDR3 model.