diff --git a/User-Documentation.md b/User-Documentation.md
index 33ab1d6..96db3c5 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -14,7 +14,7 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to
 | ROW_BITS     | width of row address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `12` to `16`.     |
 | COL_BITS     | width of column address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `10` to `12`.     |
 | BA_BITS     | width of bank address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Usual value is `3`.      |
-| DQ_BITS     | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`. <sup>[1]</sup>    |
+| DQ_BITS     | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`.  <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>   |
 | LANES     | number of DDR3 device to be controlled. This depends on the DDR3 module used. <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup> |
 | AUX_WIDTH | width of auxiliary line. Value must be >= 4.  <sup>[[2]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>  |
 | WB2_ADDR_BITS | width of 2nd wishbone address bus for debugging (only relevant if SECOND_WISHBONE = 1).   |
@@ -73,12 +73,12 @@ Next are the **DDR3 I/O ports**, these will be connected directly to the top-lev
 Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
 
 ## Constraint File
-Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389), highlighted are all the DDR3 pins.
+Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389)  <sup>[[4]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>, highlighted are all the DDR3 pins. This constraint file assumes a dual-rank DDR3 RAM (thus 2 pairs of `o_ddr3_clk`, `o_ddr3_cke`, `o_ddr3_s_n`, and `o_ddr3_odt`)  with 8 lanes of x8 DDR3 (thus 8 `o_ddr3_dm`, 8 `io_ddr3_dqs`, and 64 `io_ddr3_dq`).
 
 ### Note:  
 [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.   
 [2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.  
-[3]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO). 
-
+[3]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).   
+[4]: This is the open-sourced [10Gb Ethernet Project](https://github.com/ZipCPU/eth10g).
 
 #  Verify Design 
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