diff --git a/User-Documentation.md b/User-Documentation.md
index b8c9a19..fc42c3a 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -53,7 +53,7 @@ Below are the **main wishbone ports**:
 | i_wb_sel   | Byte select for write operations. Indicates which bytes of the data bus are to be overwritten for the write operation. | 
 | o_wb_stall   | Indicates if the controller is busy (1)and cannot accept any new requests. | 
 | o_wb_ack   |  Acknowledgement signal. Indicates that a read or write request has been completed. | 
-| o_wb_data   | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`. 
+| o_wb_data   | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`. |
 
 ***
 
@@ -66,6 +66,11 @@ Below are the **auxiliary ports** associated with the main wishbone. This is not
 
 ***
 
+After main wishbone port is the **second-wishbone ports**. This interface is only for debugging-purposes and would normally not be needed thus can be  left unconnected. The ports for the second-wishbone is very much the same as the main wishbone.
+
+Finally is the **DDR3 I/O ports**
+
+
 ### Note:  
 [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.   
 [2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.