diff --git a/User-Documentation.md b/User-Documentation.md
index c31c295..b8c9a19 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -15,15 +15,15 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to
 | COL_BITS     | width of column address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `10` to `12`.     |
 | BA_BITS     | width of bank address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Usual value is `3`.      |
 | DQ_BITS     | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`. <sup>[1]</sup>    |
-| LANES     | number of DDR3 device to be controlled. This depends on the DDR3 module used. <sup>[1]</sup> |
-| AUX_WIDTH | width of auxiliary line. Value must be >= 4.  <sup>[2]</sup>  |
+| LANES     | number of DDR3 device to be controlled. This depends on the DDR3 module used. <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup> |
+| AUX_WIDTH | width of auxiliary line. Value must be >= 4.  <sup>[[2]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>  |
 | WB2_ADDR_BITS | width of 2nd wishbone address bus for debugging (only relevant if SECOND_WISHBONE = 1).   |
 | WB2_DATA_BITS  | width of 2nd wishbone data bus for debugging (only relevant if SECOND_WISHBONE = 1).  |
 | OPT_LOWPOWER  | _has no effect yet_ |
 | OPT_BUS_ABORT  | _has no effect yet_ |
 | MICRON_SIM  | set to 1 if used in Micron DDR3 model to shorten power-on sequence, otherwise 0. |
 | TEST_DATAMASK | set to 1 if datamask needs to be tested on the calibration sequence, otherwise 0. |
-| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0.  <sup>[3]</sup>  |
+| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0.  <sup>[[3]](https://github.com/AngeloJacobo/DDR3_Controller/wiki/User-Documentation#note) </sup>  |
 | SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.|