From 13aaa4b0b5ffcc9e2dfc1cb3e166a53ac006cb45 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sat, 25 Nov 2023 13:25:13 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/User-Documentation.md b/User-Documentation.md index 8339b4e..2e8b612 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -93,19 +93,19 @@ The verilog file [`rtl/ddr3_controller`](https://github.com/AngeloJacobo/DDR3_Co *** # Compile and and Simulate Design -The easiest way to compile, lint, and formally verify the design is to run [`./run_compile.sh`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/run_compile.sh) on the top-level directory. This will first run Verilator lint. Most likely this will show errors: +The easiest way to compile, lint, and formally verify the design is to run [`./run_compile.sh`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/run_compile.sh) on the top-level directory. This will first run [Verilator](https://verilator.org/guide/latest/install.html) lint. Most likely this will show errors: > %Error: rtl//ddr3_phy: Cannot find file containing module: Disregard these errors as Verilator cannot access the verilog files for Xilinx-exclusive IPs. Other than this kind of error, there should be no other errors or warning. -After Verilator lint is compilation with Yosys, this will show warnings +Next is compilation with [Yosys](https://github.com/YosysHQ/yosys), this will show warnings > Warning: Replacing memory ... with list of registers. Disregards this kind of warning as it just converts small memory elements in the design into a series of register elements. -After Yosys compilation is Icarus Verilog compilation, this should not show any warning or errors but will display the `Test Functions` to verify that the verilog-functions return the correct values, and `Controller Parameters` to verify the top-level parameters are set properly. Delay values are also shown. +After Yosys compilation is [Icarus Verilog](https://github.com/steveicarus/iverilog) compilation, this should not show any warning or errors but will display the `Test Functions` to verify that the verilog-functions return the correct values, and `Controller Parameters` to verify the top-level parameters are set properly. Delay values are also shown. -Lastly is the Symbiyosys Formal Verification, this will run the [`ddr3.sby`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/ddr3.sby). These will run multiple verification tasks and will take time (running each task might take 10 mins or so). A summary is shown at the end where all task passed: +Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/en/latest/install.html), this will run the [`ddr3.sby`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/ddr3.sby). These will run multiple verification tasks and will take some time (running each task might take 10 mins or so). A summary is shown at the end where all task passed: