diff --git a/User-Documentation.md b/User-Documentation.md
index 3d6b264..e83f88f 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -1,5 +1,5 @@
 # Specifications and Brief Description
-This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR.
+This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) but is now being designed to be a more general memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The interface is the basic Wishbone. The main usecase now is for the 10-Gigabit Ethernet Project which utilizes this controller for an 8-lane x8 DDR3 module running at 800 MHz DDR. Controller is optimized to maintain a high data throughput and continuous sequential burst operations.
 
 
 # Getting Started